XC3000FM Datasheet, PDF (30/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
General LCA Switching Characteristics
RESET
M0/M1/M2
DONE/PROG
INIT
(Output)
2 T_MR
3 T_RM
5 T_PGW
User State
6 T_PGI
Clear State
4 T_MRW
PWRDWN
V_CC (Valid)
Configuration State
Note 3
V_CCPD
X5387
Description
Symbol
Min
Max
Units
RESET (2)
M0, M1, M2 setup time required
2
T_MR
1
µs
M0, M1, M2 hold time required
3
T_RM
3
µs
RESET Width (Low) req. for Abort
4
T_MRW
6
µs
DONE/PROG Width (Low) required for Re-config. 5
T_PGW
6
µs
INIT response after D/P is pulled Low 6
T_PGI
7
µs
PWRDWN (3) Power Down V_CC
V_CCPD
2.3
V
Notes: 1. At power-up, V_cc must rise from 2.0 V to V_CC min in less than 25 ms. If this is not possible, configuration can be de-
layed by holding RESET Low until V_cc has reached 4.0 V (2.5 V for XC3000L). A very long V_cc rise time of >100 ms, or
a non-monotonically rising V_cc may require a >1-µs High level on RESET, followed by a >6-µs Low level on RESET and
D/P after V_cc has reached 4.0 V (2.5 V for XC3000L).
2. RESET timing relative to valid mode lines (M0, M1, M2) is relevant when RESET is used to delay configuration. The
specified hold time is caused by a shift-register filter slowing down the response to RESET during configuration.
3. PWRDWN transitions must occur while V_cc >4.0 V(2.5 V for XC3000L).
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