XC3000FM Datasheet, PDF (22/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Master Serial Mode
* IF READBACK IS
ACTIVATED, A
5-kΩ RESISTOR IS
REQUIRED IN
SERIES WITH M1
DURING CONFIGURATION
THE 5 kΩ M2 PULL-DOWN
RESISTOR OVERCOMES THE
INTERNAL PULL-UP,
BUT IT ALLOWS M2 TO
BE USER I/O.
GENERAL-
PURPOSE
USER I/O
PINS
*
+5 V
M0 M1 PWRDWN
DOUT
M2
HDC
LDC
INIT
TO DIN OF OPTIONAL
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
TO CCLK OF OPTIONAL
DAISY-CHAINED LCAs WITH
DIFFERENT CONFIGURATIONS
OTHER
I/O PINS
XC3000
LCA
DEVICE
TO CCLK OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
TO DIN OF OPTIONAL
SLAVE LCAs WITH IDENTICAL
CONFIGURATIONS
+5 V
RESET
RESET
DIN
CCLK
D/P
INIT
VCC
VPP
DATA
CLK
CE
SCP
CEO
OE/RESET
XC17xx
(LOW RESETS THE XC17xx ADDRESS POINTER)
DATA
CLK
CE
CASCADED
SERIAL
MEMORY
OE/RESET
X6092
Figure 21. Master Serial Mode
In Master Serial mode, the CCLK output of the lead LCA
device drives a Xilinx Serial PROM that feeds the LCA DIN
input. Each rising edge of the CCLK output increments the
Serial PROM internal address counter. This puts the next
data bit on the SPROM data output, connected to the LCA
DIN pin. The lead LCA device accepts this data on the
subsequent rising CCLK edge.
The lead LCA device then presents the preamble data
(and all data that overflows the lead device) on its DOUT
pin. There is an internal delay of 1.5 CCLK periods, which
means that DOUT changes on the falling CCLK edge, and
the next LCA device in the daisy-chain accepts data on the
subsequent rising CCLK edge.
The SPROM CE input can be driven from either LDC or
DONE . Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user-I/O, but LDC is then
restricted to be a permanently High user output. Using
DONE also avoids contention on DIN, provided the early
DONE option is invoked.
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