XC3000FM Datasheet, PDF (26/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Peripheral Mode
CONTROL ADDRESS
SIGNALS
BUS
DATA
BUS
8
M0
D0–7 _D0–7
*
M1 PWR
DWN
CCLK
+5 V
ADDRESS
DECODE
LOGIC
REPROGRAM
OC
Figure 23. Peripheral Mode.
DOUT
CS0
M2
HDC
LCA
LDC
CS1
CS2
WS
OTHER
I/O PINS
RDY/BUSY
INIT
D/P
RESET
+5 V
* IF READBACK IS
ACTIVATED, A
5 kΩ
5-kΩ RESISTOR IS
REQUIRED IN SERIES
WITH M1
OPTIONAL
DAISY-CHAINED
LCAs WITH DIFFERENT
CONFIGURATIONS
GENERAL-
PURPOSE
USER I/O
PINS
X3031
Peripheral mode uses the trailing edge of the logic AND
condition of the CS0, CS1, CS2, and WS inputs to accept
byte-wide data from a microprocessor bus. In the lead LCA
device, this data is loaded into a double-buffered UART-
like parallel-to-serial converter and is serially shifted into
the internal logic. The lead LCA device presents the
preamble data (and all data that overflows the lead device)
on the DOUT pin.
The Ready/Busy output from the lead LCA device acts as
a handshake signal to the microprocessor. RDY/BUSY
goes Low when a byte has been received, and goes High
again when the byte-wide input buffer has transferred its
information into the shift register, and the buffer is ready to
receive new data. The length of the BUSY signal depends
on the activity in the UART. If the shift register had been
empty when the new byte was received, the BUSY signal
lasts for only two CCLK periods. If the shift register was still
full when the new byte was received, the BUSY signal can
be as long as nine CCLK periods.
Note that after the last byte has been entered, only seven
of its bits are shifted out. CCLK remains High with DOUT
equal to bit 6 (the next-to-last bit) of the last byte entered.
2-128