XC3000FM Datasheet, PDF (23/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

Master Serial Mode Programming Switching Characteristics
CCLK
(Output)
Serial Data In
1 ^TDSCK
n
2 TCKDS
n+1
n+2
Serial DOUT
(Output)
n–3
n–2
n–1
n
X3223
CCLK
Speed Grade
Min
Max
Units
Description
Symbol
Data In setup
1 T_DSCK
60
ns
Data In hold
2 _CKDS
0
ns
Notes: 1. At power-up, V_CC must rise from 2.0 V to V_CC min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until V_CC has reached 4.0 V (2.5 V for the XC3000L). A very long V_CC rise time of
>100 ms, or a non-monotonically rising V_CC may require >6-µs High level on RESET, followed by a >6-µs Low
level on RESET and D/P after V_CC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode
devices is High.
3. Master-serial-mode timing is based on slave-mode testing.
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