XC3000FM Datasheet, PDF (25/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

Master Parallel Mode Programming Switching Characteristics
A0-A15
(output)
Address for Byte n
D0-D7
RCLK
(output)
CCLK
(output)
Byte
2 T_DRC
7 CCLKs
Address for Byte n + 1
1 T_RAC
3 T_RCD
CCLK
DOUT
(output)
D6
Byte n - 1
D7
X5380
RCLK
Description
To address valid
To data setup
To data hold
RCLK High
RCLK Low
Symbol
1
T_RAC
2
T_DRC
3
T_RCD
T_RCH
T_RCL
Min
0
60
0
600
4.0
Max
200
Units
ns
ns
ns
ns
µs
Notes: 1. At power-up, V_CC must rise from 2.0 V to V_CC min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until V_CC has reached 4.0 V (2.5 V for the XC3000L). A very long V_CC rise time of
>100 ms, or a non-monotonically rising V_CC may require a >6-µs High level on RESET, followed by a >6-µs Low
level on RESET and D/P after V_CC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration can be controlled by holding RESET Low with or until after the INIT of all daisy-chain slave-mode
devices is High.
This timing diagram shows that the EPROM requirements are extremely relaxed:
EPROM access time can be longer than 4000 ns. EPROM data output has no hold time requirements.
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