XC3000FM Datasheet, PDF (27/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

Peripheral Mode Programming Switching Characteristics
WS, CS0, CS1
WRITE TO LCA
CS2
D0-D7
CCLK
RDY/BUSY
DOUT
1
TCA
2
TDC
Valid
TCD
3
4 _TWTRB
TBUSY
6
D6
D7
D0
D1
D2
Previous Byte
New Byte
X3249
Description
Symbol
Min
Max
Units
Write
Effective Write time required
1
T_CA
100
ns
(Assertion of CS0, CS1, CS2, WS)
DIN Setup time required
2
T_DC
60
ns
DIN Hold time required
3
T_CD
0
ns
RDY/BUSY delay after end of WS
4
T_WTRB
60
ns
RDY
Earliest next WS after end of BUSY
5
T_RBWT
0
ns
BUSY Low time generated
6
T_BUSY
2.5
9
CCLK
Periods
Notes:
1. At power-up, V_CC must rise from 2.0 V to V_CC min in less than 25 ms. If this is not possible, configuration can be
delayed by holding RESET Low until V_CC has reached 4.0 V (2.5 V for the XC3000L). A very long V_CC rise time of
>100 ms, or a non-monotonically rising V_CC may require a >6-µs High level on RESET, followed by a >6-µs Low level
on RESET and D/P after V_CC has reached 4.0 V (2.5 V for the XC3000L).
2. Configuration must be delayed until the INIT of all LCAs is High.
3. Time from end of WS to CCLK cycle for the new byte of data depends on completion of previous byte processing and
the phase of the internal timing generator for CCLK.
4. CCLK and DOUT timing is tested in slave mode.
5. T_BUSY indicates that the double-buffered parallel-to-serial converter is not yet ready to receive new data. The shortest
T_BUSY occurs when a byte is loaded into an empty parallel-to-serial converter. The longest T_BUSY occurs when a new
word is loaded into the input register before the second-level buffer has started shifting out data.
This timing diagram shows very relaxed requirements: Data need not be held beyond the rising edge of WS. BUSY will
go active within 60 ns after the end of WS. BUSY will stay active for several microseconds. WS may be asserted immedi-
ately after the end of BUSY.
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