XC3000FM Datasheet, PDF (36/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Pin Functions During Configuration
SLAVE
<1:1:1>
PWRDWN (I)
VCC
M1 (HIGH) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
RESET (I)
DONE
VCC
DIN (I)
DOUT
CCLK (I)
GND
Configuration Mode <M2:M1:M0>
MASTER-SER
<0:0:0>
PWRDWN (I)
VCC
M1 (LOW) (I)
M0 (LOW) (I)
M2 (LOW) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
PERIPHERAL
<1:0:1>
PWRDWN (I)
VCC
M1 (LOW) (I)
M0 (HIGH) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
MASTER-HIGH
<1:1:0>
PWRDWN (I)
VCC
M1 (HIGH) (I)
M0 (LOW) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
RESET (I)
DONE
RESET (I)
DONE
DATA 7 (I)
RESET (I)
DONE
DATA 7 (I)
VCC
DIN (I)
DOUT
CCLK(O)
GND
DATA 6 (I)
DATA 5 (I)
CS0 (I)
DATA 4 (I)
VCC
DATA 3 (I)
CS1 (I)
DATA 2 (I)
DATA 1 (I)
RDY/BUSY
DATA 0 (I)
DOUT
CCLK(O)
WS (I)
CS2 (I)
GND
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
VCC
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK(O)
A0
A1
A2
A3
A15
A4
A14
A5
GND
A13
A6
A12
A7
A11
A8
A10
A9
MASTER-LOW
<1:0:0>
PWRDWN (I)
VCC
M1 (LOW) (I)
M0 (LOW) (I)
M2 (HIGH) (I)
HDC (HIGH)
LDC (LOW)
INIT*
GND
RESET (I)
DONE
DATA 7 (I)
DATA 6 (I)
DATA 5 (I)
DATA 4 (I)
VCC
DATA 3 (I)
DATA 2 (I)
DATA 1 (I)
RCLK
DATA 0 (I)
DOUT
CCLK(O)
A0
A1
A2
A3
A15
A4
A14
A5
GND
A13
A6
A12
A7
A11
A8
A10
A9
***
****
44 68 84 84 100 100 132 160 175 208
PLCC PLCC PLCC PGA PQFP TQFP PGA PQFP PGA PQFP
7 10 12 B2 29 26 A1 159 B2 3
12 18 22 F3 41 38 C8 20 D9 26
16 25 31 J2 52 49 B13 40 B14 48
17 26 32 L1 54 51 A14 42 B15 50
18 27 33 K2 56 53 C13 44 C15 56
19 28 34 K3 57 54 B14 45 E14 57
20 30 36 L3 59 56 D14 49 D16 61
22 34 42 K6 65 62 G14 59 H15 77
23 35 43 J6 66 63 H12 19 J14 79
26 43 53 L11 76 73 M13 76 P15 100
27 44 54 K10 78 75 P14 78 R15 102
28 45 55 J10 80 77 N13 80 R14 107
46 56 K11 81 78 M12 81 N13 109
30 47 57 J11 82 79 P13 82 T14 110
48 58 H10 83 80 N11 86 P12 115
49 60 F10 87 84 M9 92 T11 122
50 61 G10 88 85 N9 93 R10 123
51 62 G11 89 86 N8 98 R9 128
34 52 64 F9 91 88 M8 100 N9 130
53 65 F11 92 89 N7 102 P8 132
54 66 E11 93 90 P6 103 R8 133
55 67 E10 94 91 M6 108 R7 138
56 70 D10 98 95 M5 114 R5 145
57 71 C11 99 96 N4 115 P5 146
38 58 72 B11 100 97 N2 119 R3 151
39 59 73 C10 1 98 M3 120 N4 152
40 60 74 A11 2 99 P1 121 R2 153
61 75 B10 5
2 M2 124 P2 161
62 76 B9 6
3 N1 125 M3 162
63 77 A10 8
5 L2 128 P1 165
64 78 A9 9
6 L1 129 N1 166
65 81 B6 12 9 K1 132 M1 172
66 82 B7 13 10 J2 133 L2 173
67 83 A7 14 11 H1 136 K2 178
68 84 C7 15 12 H2 137 K1 179
1 1 1 C6 16 13 H3 139 J3 182
2 2 A6 17 14 G2 141 H2 184
3 3 A5 18 15 G1 142 H1 185
4 4 B5 19 16 F2 147 F2 192
5 5 C5 20 17 E1 148 E1 193
6 8 A3 23 20 D1 151 D1 199
7 9 A2 24 21 D2 152 C1 200
8 10 B3 25 22 B1 155 E3 203
9 11 A1 26 26 C2 156 C2 204
XXXX
X XXXXX
XXX XX
X**
X
X**
XX X
X**
XX X
User
Operation
PWRDWN (I)
VCC
RDATA
RTRIG (I)
I/O
I/O
I/O
I/O
GND
XTL2 OR I/O
RESET (I)
PROGRAM (I)
I/O
XTL1 OR I/O
I/O
I/O
I/O
I/O
Vcc
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CCLK (I)
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
All Others
XC3020 etc.
XC3030 etc.
XC3042 etc.
XC3064 etc.
XC3090 etc.
XC3195
X5266
Represents a 50-kΩ to 100-kΩ pull-up before and during configuration
* INIT is an open drain output during configuration
(I) Represents an input
** Pin assignmnent for the XC3064/XC3090 and XC3195 differ from those shown. See page 2-138.
*** Peripheral mode and master parallel mode are not supported in the PC44 package. See page 2-135.
**** Pin assignments for the XC3195 PQ208 differ from those shown. See page 2-146.
Pin assignments of PGA Footprint PLCC sockets and PGA packages are not electrically identical.
Generic I/O pins are not shown.
The information on this page is provided as a convenient summary. For detailed pin descriptions, see the preceding two pages.
For a detailed description of the configuration modes, see pages 2-190 through 2-200.
For pinout details, see pages 2-136 through 2-146.
Before and during configuration, all outputs that are not used for the configuration process are 3-stated with
a 50 kΩ to 100 kΩ pull-up resistor.
2-138