XC3000FM Datasheet, PDF (38/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
XC3000 Family 44-Pin PLCC Pinouts
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
XC3030
GND
I/O
I/O
I/O
I/O
I/O
PWRDWN
TCLKIN-I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
M1-RDATA
M0-RTRIG
M2-I/O
HDC-I/O
LDC-I/O
I/O
INIT-I/O
Pin No.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
Peripheral mode and Master Parallel mode are not supported in the PC44 package
XC3030
GND
I/O
I/O
XTL2(IN)-I/O
RESET
DONE-PGM
I/O
XTL1(OUT)-BCLK-I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
DIN-I/O
DOUT-I/O
CCLK
I/O
I/O
I/O
I/O
XC3030 Family 64-Pin Plastic VQFP Pinouts
XC3000, XC3000A, XC3000L and XC3100 families have identical pinouts
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
XC3030
A0-WS-I/O
A1-CS2-I/O
A2-I/O
A3-I/O
A4-I/O
A14-I/O
A5-I/O
GND
A13-I/O
A6-I/O
A12-I/O
A7-I/O
A11-I/O
A8-I/O
A10-I/O
A9-I/O
PWRDN
TCLKIN-I/O
I/O
I/O
I/O
I/O
I/O
VCC
I/O
I/O
I/O
I/O
I/O
I/O
M1-RDATA
M0-RTRIG
Pin No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
XC3030
M2-I/O
HDC-I/O
I/O
LDC-I/O
I/O
I/O
I/O
INIT-I/O
GND
I/O
I/O
I/O
I/O
I/O
XTAL2(IN)-I/O
RESET
DONE-PG
D7-I/O
XTAL1(OUT)-BCLKIN-I/O
D6-I/O
D5-I/O
CS0-I/O
D4-I/O
VCC
D3-I/O
CS1-I/O
D2-I/O
D1-I/O
RDY/BUSY-RCLK-I/O
D0-DIN-I/O
DOUT-I/O
CCLK
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