XC3000FM Datasheet, PDF (21/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

configuration program can be used to enable the IOB pull-
up resistors in the Operational mode to act either as an
input load or to avoid a floating input on an otherwise
unused pin.
Readback
The contents of a Logic Cell Array may be read back if it
has been programmed with a bitstream in which the
Readback option has been enabled. Readback may be
used for verification of configuration and as a method of
determining the state of internal logic nodes during debug-
ging. There are three options in generating the configura-
tion bitstream.
• “Never” inhibits the Readback capability.
• “One-time,” inhibits Readback after one Readback
has been executed to verify the configuration.
• “On-command” allows unrestricted use of Readback.
Readback is accomplished without the use of any of the
user I/O pins; only M0, M1 and CCLK are used. The
initiation of Readback is produced by a Low to High
transition of the M0/RTRIG (Read Trigger) pin. The CCLK
input must then be driven by external logic to read back the
configuration data. The first three Low-to-High CCLK
transitions clock out dummy data. The subsequent Low-
to-High CCLK transitions shift the data frame information
out on the M1/RDATA (Read Data) pin. Note that the logic
polarity is always inverted, a zero in configuration be-
comes a one in Readback, and vice versa. Note also that
each Readback frame has one Start bit (read back as a
one) but, unlike in configuration, each Readback frame
has only one Stop bit (read back as a zero). The third
leading dummy bit mentioned above can be considered
the Start bit of the first frame. All data frames must be read
back to complete the process and return the Mode Select
and CCLK pins to their normal functions.
Readback data includes the current state of each CLB
flip-flop, each input flip-flop or latch, and each device pad.
These data are imbedded into unused configuration bit
positions during Readback. This state information is used
by the XACT development system In-Circuit Verifier to
provide visibility into the internal operation of the logic
while the system is operating. To readback a uniform time-
sample of all storage elements, it may be necessary to
inhibit the system clock.
Reprogram
To initiate a re-programming cycle, the dual-function pin
DONE/PROG must be given a High-to-Low transition. To
reduce sensitivity to noise, the input signal is filtered for two
cycles of the LCA device internal timing generator. When
reprogram begins, the user-programmable I/O output buff-
ers are disabled and high-impedance pull-ups are pro-
vided for the package pins. The device returns to the Clear
state and clears the configuration memory before it indi-
cates ‘initialized’. Since this Clear operation uses chip-
individual internal timing, the master might complete the
Clear operation and then start configuration before the
slave has completed the Clear operation. To avoid this
problem, the slave INIT pins must be AND-wired and used
to force a RESET on the master (see Figure 22). Repro-
gram control is often implemented using an external open-
collector driver which pulls DONE/PROG Low. Once a
stable request is recognized, the DONE/PROG pin is held
Low until the new configuration has been completed. Even
if the re-program request is externally held Low beyond the
configuration period, the LCA device will begin operation
upon completion of configuration.
DONE Pull-up
DONE/PROG is an open-drain I/O pin that indicates the
LCA device is in the operational state. An optional internal
pull-up resistor can be enabled by the user of the XACT
development system when MAKEBITS is executed. The
DONE/PROG pins of multiple LCA devices in a daisy-
chain may be connected together to indicate all are DONE
or to direct them all to reprogram.
DONE Timing
The timing of the DONE status signal can be controlled by
a selection in the MakeBits program to occur either a CCLK
cycle before, or after, the outputs going active. See Figure
20. This facilitates control of external functions such as a
PROM enable or holding a system in a wait state.
RESET Timing
As with DONE timing, the timing of the release of the
internal reset can be controlled by a selection in the
MakeBits program to occur either a CCLK cycle before, or
after, the outputs going active. See Figure 20. This reset
keeps all user programmable flip-flops and latches in a
zero state during configuration.
Crystal Oscillator Division
A selection in the MakeBits program allows the user to
incorporate a dedicated divide-by-two flip-flop between
the crystal oscillator and the alternate clock line. This
guarantees a symmetrical clock signal. Although the fre-
quency stability of a crystal oscillator is very good, the
symmetry of its waveform can be affected by bias or
feedback drive.
The following seven pages describe the different configuration modes in detail
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