XC3000FM Datasheet, PDF (45/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

PGA Pin
Number
B2
D4
B3
C4
B4
A4
D5
C5
B5
A5
C6
D6
B6
A6
B7
C7
D7
A7
A8
B8
C8
D8
D9
C9
B9
A9
A10
D10
C10
B10
A11
B11
D11
C11
A12
B12
C12
D12
A13
B13
C13
A14
XC3000 Families 175-Pin Ceramic and Plastic PGA Pinouts
XC3000, XC3000A, XC3000L, XC3100 and XC3100A families have identical pinouts
XC3090, XC3195
PWRDN
TCLKIN-I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PGA Pin
Number
D13
B14
C14
B15
D14
C15
E14
B16
D15
C16
D16
F14
E15
E16
F15
F16
G14
G15
G16
H16
H15
H14
J14
J15
J16
K16
K15
K14
L16
L15
M16
M15
L14
N16
P16
N15
R16
M14
P15
N14
R15
P14
XC3090, XC3195
I/O
M1-RDATA
GND
M0-RTRIG
VCC
M2-I/O
HDC-I/O
I/O
I/O
I/O
LDC-I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
INIT-I/O
VCC
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
XTL2(IN)-I/O
GND
RESET
VCC
PGA Pin
Number
R14
N13
T14
P13
R13
T13
N12
P12
R12
T12
P11
N11
R11
T11
R10
P10
N10
T10
T9
R9
P9
N9
N8
P8
R8
T8
T7
N7
P7
R7
T6
R6
N6
P6
T5
R5
P5
N5
T4
R4
P4
XC3090, XC3195
DONE-PG
D7-I/O
XTL1(OUT)-BCLKIN-I/O
I/O
I/O
I/O
I/O
D6-I/O
I/O
I/O
I/O
I/O
I/O
D5-I/O
CS0-I/O
I/O
I/O
I/O
I/O
D4-I/O
I/O
VCC
GND
D3-I/O
CS1-I/O
I/O
I/O
I/O
I/O
D2-I/O
I/O
I/O
I/O
I/O
I/O
D1-I/O
RDY/BUSY-RCLK-I/O
I/O
I/O
I/O
I/O
PGA Pin
Number
R3
N4
R2
P3
N3
P2
M3
R1
N2
P1
N1
L3
M2
M1
L2
L1
K3
K2
K1
J1
J2
J3
H3
H2
H1
G1
G2
G3
F1
F2
E1
E2
F3
D1
C1
D2
B1
E3
C2
D3
C3
XC3090, XC3195
D0-DIN-I/O
DOUT-I/O
CCLK
VCC
GND
A0-WS-I/O
A1-CS2-I/O
I/O
I/O
A2-I/O
A3-I/O
I/O
I/O
A15-I/O
A4-I/O
I/O
I/O
A14-I/O
A5-I/O
I/O
I/O
GND
VCC
A13-I/O
A6-I/O
I/O
I/O
I/O
I/O
A12-I/O
A7-I/O
I/O
I/O
A11-I/O
A8-I/O
I/O
I/O
A10-I/O
A9-I/O
VCC
GND
Unprogrammed IOBs have a default pull-up. This prevents an undefined pad level for unbonded or unused IOBs. Programmed
outputs are default slew-rate limited.
Pins A2, A3, A15, A16, T1, T2, T3, T15 and T16 are not connected. Pin A1 does not exist.
2-147