XC3000FM Datasheet, PDF (14/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Control of the 3-state input by the same signal that drives
the buffer input, creates an open-drain wired-AND func-
tion. A logic High on both buffer inputs creates a high
impedance, which represents no contention. A logic Low
enables the buffer to drive the Longline Low. See Figure
15b. Pull-up resistors are available at each end of the
Longline to provide a High output when all connected
buffers are non-conducting. This forms fast, wide gating
functions. When data drives the inputs, and separate
signals drive the 3-state control lines, these buffers form
multiplexers (3-state busses). In this case, care must be
used to prevent contention through multiple active buffers
X1244
Figure 14. Programmable Interconnection of Longlines. This is provided at the edges of the routing area. Three-state buffers
allow the use of horizontal Longlines to form on-chip wired AND and multiplexed buses. The left two non-clock vertical Longlines
per column (except XC3020) and the outer perimeter Longlines may be programmed as connectible half-length lines.
V_CC
Z = D_A • D_B • D_C • _... • D_N
V_CC
(LOW)
D_A
D_B
D_C
D_N
Figure 15a. 3-State Buffers Implement a Wired-AND Function. When all the buffer 3-state
lines are High, (high impedance), the pull-up resistor(s) provide the High output. The buffer
inputs are driven by the control signals or a Low.
T
X3036
OE
Z = D_A • A + D_B • B + D_C • C + … + D_N • N
D_A
D_B
D_C
D_N
WEAK
KEEPER
A
B
C
N
CIRCUIT
X1741
Figure 15b. 3-State Buffers Implement a Multiplexer. The selection is accomplished by the buffer 3-state signal.
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