XC3000FM Datasheet, PDF (28/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Slave Serial Mode
Micro
Computer
STRB
D0
D1
I/O
D2
Port
D3
D4
D5
D6
D7
RESET
+5 V
*
M0 M1 PWRDWN
+5 V
CCLK
DIN
M2
DOUT
HDC
LDC
LCA
D/P
INIT
RESET
Other
I/O Pins
* _{If Readback is}
Activated, a
5-kΩ Resistor is
Required in
Series with M1
5 kΩ
Optional
Daisy-Chained
LCAs with
Different
Configurations
General-
Purpose
User I/O
Pins
Figure 24. Slave Serial Mode.
In Slave Serial mode, an external signal drives the CCLK
input(s) of the LCA device(s). The serial configuration
bitstream must be available at the DIN input of the lead
LCA device a short set-up time before each rising CCLK
edge. The lead LCA device then presents the preamble
X3157
data (and all data that overflows the lead device) on its
DOUT pin. There is an internal delay of 0.5 CCLK periods,
which means that DOUT changes on the falling CCLK
edge, and the next LCA device in the daisy-chain accepts
data on the subsequent rising CCLK edge.
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