XC3000FM Datasheet, PDF (3/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

IMPORTANT NOTICE
XC3000, XC3000A, XC3000L,
®
All new designs should use XC3000A or
XC3100A. Information on XC3000 and
XC3100 is presented here as reference
XC3100, XC3100A
for existing designs.
Logic Cell Array Families
Product Description
Features
• Complete line of five related Field Programmable
Gate Array product families
– XC3000, XC3000A, XC3000L, XC3100, XC3100A
• Ideal for a wide range of custom VLSI design tasks
– Replaces TTL, MSI, and other PLD logic
– Integrates complete sub-systems into a single
package
– Avoids the NRE, time delay, and risk of
conventional masked gate arrays
• High-performance CMOS static memory technology
– Guaranteed toggle rates of 70 to 325 MHz, logic
delays from 9 to 2.2 ns
– System clock speeds over 80 MHz
– Low quiescent and active power consumption
• Flexible FPGA architecture
– Compatible arrays ranging from 1,000 to 7,500
gate complexity
– Extensive register, combinatorial, and I/O
capabilities
– High fan-out signal distribution, low-skew clock
nets
– Internal 3-state bus capabilities
– TTL or CMOS input thresholds
– On-chip crystal oscillator amplifier
• Unlimited reprogrammability
– Easy design iteration
– In-system logic changes
• Extensive Packaging Options
– Over 20 different packages
– Plastic and ceramic surface-mount and pin-grid-
array packages
– Thin and Very Thin Quad Flat Pack (TQFP and
VQFP) options
• Ready for volume production
– Standard, off-the-shelf product availability
– 100% factory pre-tested devices
– Excellent reliability record
• Complete XACT Development System
– Schematic capture, automatic place and route
– Logic and timing simulation
– Interactive design editor for design optimization
– Timing calculator
– Interfaces to popular design environments like
Viewlogic, Cadence, Mentor Graphics, and others
Description
The CMOS XC3000 Class of Logic Cell Array (LCA)
families provide a group of high-performance, high-den-
sity, digital integrated circuits. Their regular, extendable,
flexible, user-programmable array architecture is com-
posed of a configuration program store plus three types of
configurable elements: a perimeter of I/O Blocks (IOBs), a
core array of Configurable Logic Bocks (CLBs) and re-
sources for interconnection. The general structure of an
LCA device is shown in Figure 1 on the next page. The
XACT development system provides schematic capture
and auto place-and-route for design entry. Logic and
timing simulation, and in-circuit emulation are available as
design verification alternatives. The design editor is used
for interactive design optimization, and to compile the data
pattern that represents the configuration program.
The LCA user logic functions and interconnections are
determined by the configuration program data stored in
internal static memory cells. The program can be loaded in
any of several modes to accommodate various system
requirements. The program data resides externally in an
EEPROM, EPROM or ROM on the application circuit
board, or on a floppy disk or hard disk. On-chip initialization
logic provides for optional automatic loading of program
data at power-up. The companion XC17XX Serial
Configuration PROMs provide a very simple serial config-
uration program storage in a one-time programmable
package.
Device
XC3020, 3020A, 3020L, 3120, 3120A
XC3030, 3030A, 3030L, 3130, 3130A
XC3042, 3042A, 3042L, 3142, 3142A
XC3064, 3064A, 3064L, 3164, 3164A
XC3090, 3090A, 3090L, 3190, 3190A
XC3195, 3195A
CLBs
64
100
144
224
320
484
Array
8x8
10 x 10
12 x 12
16 x 14
16 x 20
22 x 22
User I/Os
Max
64
80
96
120
144
176
Flip-Flops
256
360
480
688
928
1,320
Horizontal
Longlines
16
20
24
32
40
44
Configuration
Data Bits
14,779
22,176
30,784
46,064
64,160
94,984
2-105