XC3000FM Datasheet, PDF (24/50 Pages) Xilinx, Inc – XC3000 Logic Cell Array Families

XC3000, XC3000A, XC3000L, XC3100, XC3100A Logic Cell Array Families
Master Parallel Mode
* If Readback is ^{+5 V}
Activated, a
5-kΩ Resistor is
Required in
Series With M1
5 kΩ
General-
Purpose
User I/O
Pins
Reprogram
System Reset
* ^{+5 V}
M0 M1PWRDWN
CCLK
DOUT
M2
HDC
RCLK
A15
A14
A13
A12
Other
I/O Pins
A11
LCA A10
Master _A9
D7
A8
D6
A7
D5
A6
D4
A5
D3
A4
D2
A3
D1
A2
D0
A1
RESET
A0
D/P
INIT _N.C.
+5 V
*
+5 V
*
M0 M1PWRDWN
M0 M1PWRDWN
A15
A14
A13
A12 ^EPROM
A11
A10
A9
A8
A7
D7
A6
D6
A5
D5
A4
D4
A3
D3
A2
D2
A1
D1
A0
D0
OE
CE
8
Open
Collector
CCLK
DIN
DOUT
LCA
Slave #1
M2
HDC
LDC
Other
I/O Pins
5 kΩ
...
General-
Purpose
User I/O
Pins
CCLK
DIN
DOUT
LCA
Slave #n
M2
HDC
LDC
Other
I/O Pins
5 kΩ
General-
Purpose
User I/O
Pins
INIT
D/P
RESET
INIT
D/P
Reset
Note: XC2000 Devices Do Not
Have INIT to Hold Off a Master
Device. Reset of a Master Device
Should be Asserted by an External
Timing Circuit to Allow for LCA CCLK
Variations in Clear State Time.
+5 V
5 kΩ Each
X3159
Figure 22. Master Parallel Mode
In Master Parallel mode, the lead LCA device directly
addresses an industry-standard byte-wide EPROM and
accepts eight data bits right before incrementing (or
decrementing) the address outputs.
The eight data bits are serialized in the lead LCA device,
which then presents the preamble data (and all data that
overflows the lead device) on the DOUT pin. There is an
internal delay of 1.5 CCLK periods, after the rising CCLK
edge that accepts a byte of data, and also changes the
EPROM address, until the falling CCLK edge that makes
the LSB (D0) of this byte appear at DOUT. This means that
DOUT changes on the falling CCLK edge, and the next
LCA device in the daisy chain accepts data on the subse-
quent rising CCLK edge.
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