DS705 Datasheet, PDF (53/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
IEEE 1149.1/1553 JTAG Test Access Port Timing
X-Ref Target - Figure 15
TCK
(Input)
TMS
(Input)
T_TMSTCK
T_TDITCK
T_TCKTMS
T_TCKTDI
T_CCH
T_CCL
1/F_TCK
TDI
(Input)
TDO
(Output)
T_TCKTDO
Figure 15: JTAG Waveforms
DS705_16_061908
Table 57: Timing for the JTAG Test Access Port
Symbol
Description
Min
Clock-to-Output Times
T_TCKTDO The time from the falling transition on the TCK pin to data appearing at the TDO pin
1.0
Setup Times
T_TDITCK The time from the setup of data at the All functions except those shown below
7.0
TDI pin to the rising transition at the
TCK pin
Boundary-Scan commands
13.0
(INTEST, EXTEST, SAMPLE)
T_TMSTCK The time from the setup of a logic level at the TMS pin to the rising transition at the TCK pin
7.0
Hold Times
T_TCKTDI The time from the rising transition at All functions except those shown below
0
the TCK pin to the point when data is
last held at the TDI pin
Configuration commands (CFG_IN, ISC_PROGRAM)
3.5
T_TCKTMS The time from the rising transition at the TCK pin to the point when a logic level is last held at the
0
TMS pin
Clock Timing
T_CCH
The High pulse width at the TCK pin All functions except ISC_DNA command
5
T_CCL
The Low pulse width at the TCK pin
5
T_CCHDNA The High pulse width at the TCK pin During ISC_DNA command
10
T_CCLDNA The Low pulse width at the TCK pin
10
F_TCK
Frequency of the TCK signal
BYPASS or HIGHZ instructions
0
All operations except for BYPASS or HIGHZ instructions
Max Units
11.0 ns
–
ns
–
ns
–
ns
–
ns
–
–
10,000
10,000
33
20
ns
ns
ns
ns
MHz
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. For details on JTAG, see “JTAG Configuration Mode and Boundary-Scan” in Chapter 9 of UG332, Spartan-3 Generation Configuration User
Guide.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
53