DS705 Datasheet, PDF (22/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

R
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Output Propagation Times
Table 24: Timing for the IOB Output Path
Symbol
Description
Conditions
Clock-to-Output Times
T_IOCKP
When reading from the Output Flip-Flop
(OFF), the time from the active transition at
the OCLK input to data appearing at the
Output pin
LVCMOS25⁽²⁾, 12 mA output
drive, Fast slew rate
Propagation Times
T_IOOP
The time it takes for data to travel from the LVCMOS25⁽²⁾, 12 mA output
JOB’s O input to the Output pin
drive, Fast slew rate
T_IOOLP
The time it takes for data to travel from the
O input through the OFF latch to the
Output pin
Set/Reset Times
T_IOSRP
Time from asserting the OFF’s SR input to LVCMOS25⁽²⁾, 12 mA output
setting/resetting data at the Output pin drive, Fast slew rate
T_IOGSRQ
Time from asserting the Global Set Reset
(GSR) input on the
STARTUP_SPARTAN3A primitive to
setting/resetting data at the Output pin
Device
All
All
All
Speed Grade
-4
Max
Units
3.13
ns
2.91
ns
2.85
ns
3.89
ns
9.65
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned to the
data Output. When this is true, add the appropriate Output adjustment from Table 26.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
22