DS705 Datasheet, PDF (25/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

R
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Table 26: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
LVCMOS25
Slow 2 mA
5.33
ns
4 mA
2.90
ns
6 mA
2.91
ns
8 mA
1.22
ns
12 mA
1.22
ns
16 mA
0.90
ns
24 mA
2.31
ns
Fast 2 mA
4.71
ns
4 mA
2.19
ns
6 mA
1.49
ns
8 mA
0.39
ns
12 mA
0.00
ns
16 mA
0.01
ns
24 mA
0.01
ns
QuietIO 2 mA
25.92
ns
4 mA
25.92
ns
6 mA
25.92
ns
8 mA
15.57
ns
12 mA
15.59
ns
16 mA
14.27
ns
24 mA
11.37
ns
LVCMOS18
Slow 2 mA
5.00
ns
4 mA
3.69
ns
6 mA
2.91
ns
8 mA
2.02
ns
12 mA
1.57
ns
16 mA
1.19
ns
Fast 2 mA
4.12
ns
4 mA
2.62
ns
6 mA
1.91
ns
8 mA
1.06
ns
12 mA
0.83
ns
16 mA
0.63
ns
QuietIO 2 mA
24.97
ns
4 mA
24.97
ns
6 mA
24.08
ns
8 mA
16.43
ns
12 mA
14.52
ns
16 mA
13.41
ns
Table 26: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
Speed Grade
-4
Units
LVCMOS15
Slow 2 mA
6.41
ns
4 mA
3.97
ns
6 mA
3.21
ns
8 mA
2.53
ns
12 mA
2.06
ns
Fast 2 mA
5.83
ns
4 mA
3.05
ns
6 mA
1.95
ns
8 mA
1.60
ns
12 mA
1.30
ns
QuietIO 2 mA
34.11
ns
4 mA
25.66
ns
6 mA
24.64
ns
8 mA
22.06
ns
12 mA
20.64
ns
LVCMOS12
Slow 2 mA
7.14
ns
4 mA
4.87
ns
6 mA
5.67
ns
Fast 2 mA
6.77
ns
4 mA
5.02
ns
6 mA
4.09
ns
QuietIO 2 mA
50.76
ns
4 mA
43.17
ns
6 mA
37.31
ns
PCI33_3
0.34
ns
HSTL_I
0.85
ns
HSTL_III
1.16
ns
HSTL_I_18
0.35
ns
HSTL_II_18
0.30
ns
HSTL_III_18
0.47
ns
SSTL18_I
0.40
ns
SSTL18_II
0.30
ns
SSTL2_I
0.00
ns
SSTL2_II
-0.05
ns
SSTL3_I
0.00
ns
SSTL3_II
0.17
ns
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
25