DS705 Datasheet, PDF (28/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Table 27: Test Methods for Timing Measurement at I/Os (Cont’d)
Signal Standard
(IOSTANDARD)
Differential
V_REF (V)
Inputs
V_L (V)
V_H (V)
Outputs
R_T (Ω)
V_T (V)
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
-
V_ICM – 0.125 V_ICM + 0.125
50
-
V_ICM – 0.125 V_ICM + 0.125
50
-
V_ICM – 0.125 V_ICM + 0.125
1M
-
V_ICM – 0.125 V_ICM + 0.125
50
-
V_ICM – 0.125 V_ICM + 0.125
50
-
V_ICM – 0.3
V_ICM + 0.3
N/A
-
V_ICM – 0.3
V_ICM + 0.3
N/A
-
V_ICM – 0.1
V_ICM + 0.1
50
-
V_ICM – 0.1
V_ICM + 0.1
50
-
V_ICM – 0.1
V_ICM + 0.1
50
-
V_ICM – 0.1
V_ICM + 0.1
50
-
V_ICM – 0.1
V_ICM + 0.1
50
0.9
V_REF – 0.5
V_REF + 0.5
50
0.9
V_REF – 0.5
V_REF + 0.5
50
1.1
V_REF – 0.5
V_REF + 0.5
50
0.9
V_REF – 0.5
V_REF + 0.5
50
0.9
V_REF – 0.5
V_REF + 0.5
50
0.9
V_REF – 0.5
V_REF + 0.5
50
0.9
V_REF – 0.5
V_REF + 0.5
50
1.25
V_REF – 0.5
V_REF + 0.5
50
1.25
V_REF – 0.5
V_REF + 0.5
50
1.5
V_REF – 0.5
V_REF + 0.5
50
1.5
V_REF – 0.5
V_REF + 0.5
50
1.2
1.2
0
1.2
1.2
N/A
N/A
1.2
1.2
3.3
0.8
0.8
0.9
0.9
1.8
0.9
0.9
0.9
0.9
1.25
1.25
1.5
1.5
Notes:
1. Descriptions of the relevant symbols are as follows:
V_REF – The reference voltage for setting the input switching threshold
V_ICM – The common mode input voltage
V_M – Voltage of measurement point on signal transition
V_L – Low-level test voltage at Input pin
V_H – High-level test voltage at Input pin
R_T – Effective termination resistance, which takes on a value of 1 MΩ when no parallel termination is required
V_T – Termination voltage
2. The load capacitance (C_L) at the Output pin is 0 pF for all signal standards.
3. According to the PCI specification.
Inputs and
Outputs
V_M (V)
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_ICM
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
V_REF
The capacitive load (C_L) is connected between the output
and GND. The Output timing for all standards, as published
in the speed files and the data sheet, is always based on a
C_L value of zero. High-impedance probes (less than 1 pF)
are used for all measurements. Any delay that the test
fixture might contribute to test measurements is subtracted
from those measurements to produce the final timing
numbers as published in the speed files and data sheet.
Using IBIS Models to Simulate Load
Conditions in Application
IBIS models permit the most accurate prediction of timing
delays for a given application. The parameters found in the
IBIS model (V_REF, R_REF, and V_MEAS) correspond directly
with the parameters used in Table 27 (V_T, R_T, and V_M). Do
not confuse V_REF (the termination voltage) from the IBIS
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
28