English
Language : 

DS705 Datasheet, PDF (44/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation
R
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Configuration and JTAG Timing
General Configuration Power-On/Reconfigure Timing
X-Ref Target - Figure 10
VCCINT
(Supply)
1.0V
VCCAUX
(Supply)
2.0V
VCCO Bank 2
(Supply)
PROG_B
(Input)
INIT_B
(Open-Drain)
2.0V
TPOR
TPROG
TPL
CCLK
(Output)
TICCK
Notes:
1. The VCCINT, VCCAUX, and VCCO supplies can be applied in any order.
2. The Low-going pulse on PROG_B is optional after power-on.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 10: Waveforms for Power-On and the Beginning of Configuration
1.2V
2.5V
or
3.3V
2.5V
or
3.3V
DS705_11_061908
Table 46: Power-On Timing and the Beginning of Configuration
Symbol
Description
Device
Min
Max
Units
TPOR(2)
The time from the application of VCCINT, VCCAUX, and VCCO
All
Bank 2 supply voltage ramps (whichever occurs last) to the
rising transition of the INIT_B pin
-
18
ms
TPROG
TPL(2)
The width of the low-going pulse on the PROG_B pin
All
0.5
-
μs
The time from the rising edge of the PROG_B pin to the
All
rising transition on the INIT_B pin
-
2
ms
TINIT
TICCK(3)
Minimum Low pulse width on INIT_B output
All
300
-
ns
The time from the rising edge of the INIT_B pin to the
All
0.5
4
μs
generation of the configuration clock signal at the CCLK
output pin
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8. This means power must be applied to all VCCINT, VCCO,
and VCCAUX lines.
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only to the SPI and BPI modes.
4. For details on configuration, see UG332, Spartan-3 Generation Configuration User Guide.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
44