DS705 Datasheet, PDF (34/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Clock Buffer/Multiplexer Switching Characteristics
Table 33: Clock Distribution Switching Characteristics
Description
Symbol
Global clock buffer (BUFG, BUFGMUX, BUFGCE) I input to O-output delay
Global clock multiplexer (BUFGMUX) select S-input setup to I0 and I1 inputs.
Same as BUFGCE enable CE-input
T_GIO
T_GSI
Frequency of signals distributed on global buffers (all sides)
F_BUFG
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
Minimum Maximum
-
0.23
-
0.63
0
334
Units
ns
ns
MHz
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
34