DS705 Datasheet, PDF (45/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Configuration Clock (CCLK) Characteristics
Table 47: CCLK Output Period by ConfigRate Option Setting
Symbol
Description
ConfigRate
Setting
Temperature
Range
T_CCLK1
CCLK clock period by
ConfigRate setting
1
(power-on value)
I-Grade/
Q-Grade
T_CCLK3
3
I-Grade/
Q-Grade
T_CCLK6
6
I-Grade/
Q-Grade
T_CCLK7
7
I-Grade/
Q-Grade
T_CCLK8
8
I-Grade/
Q-Grade
T_CCLK10
10
I-Grade/
Q-Grade
T_CCLK12
12
I-Grade/
Q-Grade
T_CCLK13
13
I-Grade/
Q-Grade
T_CCLK17
17
I-Grade/
Q-Grade
T_CCLK22
22
I-Grade/
Q-Grade
T_CCLK25
25
I-Grade/
Q-Grade
T_CCLK27
27
I-Grade/
Q-Grade
T_CCLK33
33
I-Grade/
Q-Grade
T_CCLK44
44
I-Grade/
Q-Grade
T_CCLK50
50
I-Grade/
Q-Grade
T_CCLK100
100
I-Grade/
Q-Grade
Notes:
1. Set the ConfigRate option value when generating a configuration bitstream.
Minimum
1,180
390
195
168
147
116
97
88
68
51
45
42
34
25
21
10.6
Maximum
2,500
833
417
357
313
250
208
192
147
114
100
93
76
57
50
25
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
45