DS705 Datasheet, PDF (19/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Table 20: Setup and Hold Times for the IOB Input Path (Cont’d)
Symbol
Description
Conditions
T_IOICKPD
Time from the active transition at the ICLK input
of the Input Flip-Flop (IFF) to the point where
data must be held at the Input pin. The Input
Delay is programmed.
LVCMOS25⁽²⁾
Set/Reset Pulse Width
T_{RPW_IOB} Minimum pulse width to SR control input on -
IOB
IFD_DELAY_
VALUE
Device
1
XA3SD1800A
2
3
4
5
6
7
8
1
XA3SD3400A
2
3
4
5
6
7
8
-
All
Speed Grade
-4
Min
-1.40
-2.11
-2.48
-2.77
-2.62
-3.06
-3.42
-3.65
-1.31
-1.88
-2.44
-2.89
-2.83
-3.33
-3.63
-3.96
1.61
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 27 and are based on the operating conditions set forth in
Table 8 and Table 11.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, add the
appropriate Input adjustment from Table 23.
3. These hold times require adjustment whenever a signal standard other than LVCMOS25 is assigned to the data Input. If this is true, subtract
the appropriate Input adjustment from Table 23. When the hold time is negative, it is possible to change the data before the clock’s active
edge.
Table 21: Sample Window (Source Synchronous)
Symbol
Description
Max
T_SAMP Setup and hold
capture window of
an IOB flip-flop
The input capture sample window value is highly specific to a particular application, device,
package, I/O standard, I/O placement, DCM usage, and clock buffer. Please consult the
appropriate Xilinx Answer Record for application-specific values.
• Answer Record 30879
Units
ps
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
19