DS705 Datasheet, PDF (21/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

R
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Input Timing Adjustments
Table 23: Input Timing Adjustments by IOSTANDARD
Convert Input Time from
LVCMOS25 to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
-4
Units
Single-Ended Standards
LVTTL
0.62
ns
LVCMOS33
0.54
ns
LVCMOS25
0.00
ns
LVCMOS18
0.83
ns
LVCMOS15
0.60
ns
LVCMOS12
0.31
ns
PCI33_3
0.45
ns
HSTL_I
0.72
ns
HSTL_III
0.85
ns
HSTL_I_18
0.69
ns
HSTL_II_18
0.83
ns
HSTL_III_18
0.79
ns
SSTL18_I
0.71
ns
SSTL18_II
0.71
ns
SSTL2_I
0.71
ns
SSTL2_II
0.71
ns
SSTL3_I
0.78
ns
SSTL3_II
0.78
ns
Table 23: Input Timing Adjustments by IOSTANDARD (Cont’d)
Convert Input Time from
LVCMOS25 to the Following
Signal Standard (IOSTANDARD)
Add the
Adjustment
Below
-4
Units
Differential Standards
LVDS_25
0.79
ns
LVDS_33
0.79
ns
BLVDS_25
0.79
ns
MINI_LVDS_25
0.84
ns
MINI_LVDS_33
0.84
ns
LVPECL_25
0.80
ns
LVPECL_33
0.80
ns
RSDS_25
0.83
ns
RSDS_33
0.83
ns
TMDS_33
0.80
ns
PPDS_25
0.81
ns
PPDS_33
0.81
ns
DIFF_HSTL_I_18
0.80
ns
DIFF_HSTL_II_18
0.98
ns
DIFF_HSTL_III_18
1.05
ns
DIFF_HSTL_I
0.77
ns
DIFF_HSTL_III
1.05
ns
DIFF_SSTL18_I
0.76
ns
DIFF_SSTL18_II
0.76
ns
DIFF_SSTL2_I
0.77
ns
DIFF_SSTL2_II
0.77
ns
DIFF_SSTL3_I
1.06
ns
DIFF_SSTL3_II
1.06
ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating conditions
set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert input path times
originally specified for the LVCMOS25 standard to times that
correspond to other signal standards.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
21