DS705 Datasheet, PDF (18/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Input Setup and Hold Times
Table 20: Setup and Hold Times for the IOB Input Path
Symbol
Description
Conditions
Setup Times
T_IOPICK
Time from the setup of data at the Input pin to
the active transition at the ICLK input of the
Input Flip-Flop (IFF). No Input Delay is
programmed.
T_IOPICKD
Time from the setup of data at the Input pin to
the active transition at the ICLK input of the
Input Flip-Flop (IFF). The Input Delay is
programmed.
LVCMOS25⁽²⁾
LVCMOS25⁽²⁾
Hold Times
T_IOICKP
Time from the active transition at the ICLK input
of the Input Flip-Flop (IFF) to the point where
data must be held at the Input pin. No Input
Delay is programmed.
LVCMOS25⁽²⁾
IFD_DELAY_
VALUE
Device
0
XA3SD1800A
XA3SD3400A
1
XA3SD1800A
2
3
4
5
6
7
8
1
XA3SD3400A
2
3
4
5
6
7
8
0
XA3SD1800A
XA3SD3400A
Speed Grade
-4
Min
1.81
1.88
2.24
2.83
3.64
4.20
4.16
5.09
6.02
6.63
2.44
3.02
3.81
4.39
4.26
5.08
5.95
6.55
-0.52
-0.56
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
18