DS705 Datasheet, PDF (42/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

R
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DNA Port Timing
Table 44: DNA_PORT Interface Timing
Symbol
Description
T_DNASSU
T_DNASH
T_DNADSU
T_DNADH
T_DNARSU
T_DNARH
T_DNADCKO
T_DNACLKF
T_DNACLKL
T_DNACLKH
Setup time on SHIFT before the rising edge of CLK
Hold time on SHIFT after the rising edge of CLK
Setup time on DIN before the rising edge of CLK
Hold time on DIN after the rising edge of CLK
Setup time on READ before the rising edge of CLK
Hold time on READ after the rising edge of CLK
Clock-to-output delay on DOUT after rising edge of CLK
CLK frequency
CLK High time
CLK Low time
Notes:
1. The minimum READ pulse width is 5 ns, and the maximum READ pulse width is 10 μs.
Min
Max
Units
1.0
–
ns
0.5
–
ns
1.0
–
ns
0.5
–
ns
5.0
10,000
ns
0.0
–
ns
0.5
1.5
ns
0.0
100
MHz
1.0
•
ns
1.0
•
ns
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
42