DS705 Datasheet, PDF (38/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Digital Clock Manager Timing
For specification purposes, the DCM consists of three key
components: the Delay-Locked Loop (DLL), the Digital
Frequency Synthesizer (DFS), and the Phase Shifter (PS).
Aspects of DLL operation play a role in all DCM
applications. All such applications inevitably use the CLKIN
and the CLKFB inputs connected to either the CLK0 or the
CLK2X feedback, respectively. Thus, specifications in the
DLL tables (Table 37 and Table 38) apply to any application
that only employs the DLL component. When the DFS
and/or the PS components are used together with the DLL,
then the specifications listed in the DFS and PS tables
(Table 39 through Table 42) supersede any corresponding
ones in the DLL tables. DLL specifications that do not
change with the addition of DFS or PS functions are
presented in Table 37 and Table 38.
Period jitter and cycle-cycle jitter are two of many different
ways of specifying clock jitter. Both specifications describe
statistical variation from a mean value.
Period jitter is the worst-case deviation from the ideal clock
period over a collection of millions of samples. In a
histogram of period jitter, the mean value is the clock period.
Cycle-cycle jitter is the worst-case difference in clock period
between adjacent clock cycles in the collection of clock
periods sampled. In a histogram of cycle-cycle jitter, the
mean value is zero.
Delay-Locked Loop
Table 37: Recommended Operating Conditions for the DLL
Symbol
Description
Input Frequency Ranges
F_CLKIN CLKIN_FREQ_DLL
Input Pulse Requirements
Frequency of the CLKIN clock input
CLKIN_PULSE
CLKIN pulse width as a percentage of the
CLKIN period
Input Clock Jitter Tolerance and Delay Path Variation⁽⁴⁾
F_CLKIN < 150 MHz
F_CLKIN > 150 MHz
CLKIN_CYC_JITT_DLL_LF
CLKIN_CYC_JITT_DLL_HF
CLKIN_PER_JITT_DLL
Cycle-to-cycle jitter at the CLKIN input
Period jitter at the CLKIN input
F_CLKIN < 150 MHz
F_CLKIN > 150 MHz
CLKFB_DELAY_VAR_EXT
Allowable variation of off-chip feedback delay from the DCM output to
the CLKFB input
Speed Grade
-4
Min Max
5⁽²⁾
250⁽³⁾
40%
45%
60%
55%
-
±300
-
±150
-
±1
-
±1
Units
MHz
-
-
ps
ps
ns
ns
Notes:
1. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
2. The DFS, when operating independently of the DLL, supports lower FCLKIN frequencies. See Table 39.
3. To support double the maximum effective FCLKIN limit, set the CLKIN_DIVIDE_BY_2 attribute to TRUE. This attribute divides the incoming
clock period by two as it enters the DCM. The CLK2X output reproduces the clock frequency provided on the CLKIN input.
4. CLKIN input jitter beyond these limits might cause the DCM to lose lock.
5. The DCM specifications are guaranteed when both adjacent DCMs are locked.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
38