DS705 Datasheet, PDF (36/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
DSP48A Timing
To reference the DSP48A block diagram, see the XtremeDSP DSP48A for Spartan-3A DSP FPGAs User Guide (UG431).
Table 35: Setup Times for the DSP48A
Speed Grade
Symbol
Description
Pre-adder Multiplier Post-adder
-4
Units
Min
Setup Times of Data/Control Pins to the Input Register Clock
T_{DSPDCK_AA}
A input to A register CLK
-
-
-
T_{DSPDCK_DB}
D input to B register CLK
Yes
-
-
T_{DSPDCK_CC}
C input to C register CLK
-
-
-
T_{DSPDCK_DD}
D input to D register CLK
-
-
-
T_{DSPDCK_OPB} OPMODE input to B register CLK
Yes
-
-
T_{DSPDCK_OPOP} OPMODE input to OPMODE register CLK
-
-
-
Setup Times of Data Pins to the Pipeline Register Clock
0.04
ns
1.88
ns
0.05
ns
0.04
ns
0.42
ns
0.06
ns
T_{DSPDCK_AM}
T_{DSPDCK_BM}
A input to M register CLK
B input to M register CLK
-
Yes
-
Yes
Yes
-
No
Yes
-
3.79
ns
4.97
ns
3.79
ns
T_{DSPDCK_DM}
D input to M register CLK
Yes
Yes
-
T_{DSPDCK_OPM} OPMODE to M register CLK
Yes
Yes
-
Setup Times of Data/Control Pins to the Output Register Clock
5.06
ns
5.42
ns
T_{DSPDCK_AP}
T_{DSPDCK_BP}
A input to P register CLK
B input to P register CLK
-
Yes
Yes
Yes
Yes
Yes
No
Yes
Yes
5.49
ns
6.74
ns
5.48
ns
T_{DSPDCK_DP}
T_{DSPDCK_CP}
T_{DSPDCK_OPP}
D input to P register CLK
C input to P register CLK
OPMODE input to P register CLK
Yes
Yes
Yes
-
-
Yes
Yes
Yes
Yes
6.83
ns
2.18
ns
7.18
ns
Notes:
1. “Yes” means that the component is in the path. “No” means that the component is being bypassed. “-” means that no path exists, so it is not
applicable.
2. The numbers in this table are based on the operating conditions set forth in Table 8.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
36