DS705 Datasheet, PDF (40/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Digital Frequency Synthesizer
Table 39: Recommended Operating Conditions for the DFS
Symbol
Description
Input Frequency Ranges⁽²⁾
F_CLKIN CLKIN_FREQ_FX Frequency for the CLKIN input
Input Clock Jitter Tolerance⁽³⁾
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Cycle-to-cycle jitter at the CLKIN input,
based on CLKFX output frequency
CLKIN_PER_JITT_FX
Period jitter at the CLKIN input
F_CLKFX < 150 MHz
F_CLKFX > 150 MHz
Speed Grade
-4
Min Max
Units
0.2
333 MHz
-
±300 ps
-
±150 ps
-
±1
ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are used.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 37.
3. CLKIN input jitter beyond these limits may cause the DCM to lose lock.
4. The DCM specifications are guaranteed when both adjacent DCMs are locked.
Table 40: Switching Characteristics for the DFS
Speed Grade
Symbol
Description
Device
-4
Units
Min
Max
Output Frequency Ranges
CLKOUT_FREQ_FX⁽²⁾
Frequency for the CLKFX and CLKFX180 outputs
All
Output Clock Jitter^(3,4)
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX and CLKFX180
All
outputs.
CLKIN
≤ 20 MHz
Duty Cycle^(5,6)
CLKIN
> 20 MHz
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for the CLKFX and CLKFX180 outputs,
All
including the BUFGMUX and clock tree duty-cycle distortion
Phase Alignment⁽⁶⁾
CLKOUT_PHASE_FX
Phase offset between the DFS CLKFX output and the DLL
All
CLK0 output when both the DFS and DLL are used
CLKOUT_PHASE_FX180
Phase offset between the DFS CLKFX180 output and the DLL All
CLK0 output when both the DFS and DLL are used
Lock Time
LOCK_FX^(2,3)
The time from deassertion at the DCM’s
Reset input to the rising transition at its
5 MHz < F_CLKIN All
< 15 MHz
LOCKED output. The DFS asserts LOCKED
when the CLKFX and CLKFX180 signals are
F_CLKIN > 15 MHz
valid. If using both the DLL and the DFS, use
the longer locking time.
5
311
MHz
Typ
Max
Use the Spartan-3A FPGA Jitter
ps
Calculator:
www.xilinx.com/support/documentation/
data_sheets/s3a_jitter_calc.zip
±[1% of CLKFX ±[1% of CLKFX ps
period + 100]
period + 200]
-
±[1% of CLKFX ps
period + 350]
-
±200
ps
-
±[1% of CLKFX ps
period + 200]
-
5
ms
-
450
μs
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 39.
2. DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an FPGA. Output jitter strongly
depends on the environment, including the number of SSOs, the output drive strength, CLB utilization, CLB switching activities, switching frequency,
power supply and PCB design. The actual maximum output jitter depends on the system application.
5. The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
6. Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data sheet specifies a maximum
CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period is 10 ns and 1% of
10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
40