DS705 Datasheet, PDF (39/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Table 38: Switching Characteristics for the DLL
Symbol
Description
Device
Output Frequency Ranges
CLKOUT_FREQ_CLK0
Frequency for the CLK0 and CLK180 outputs
All
CLKOUT_FREQ_CLK90
Frequency for the CLK90 and CLK270 outputs
CLKOUT_FREQ_2X
Frequency for the CLK2X and CLK2X180 outputs
CLKOUT_FREQ_DV
Output Clock Jitter^(2,3,4)
Frequency for the CLKDV output
CLKOUT_PER_JITT_0
Period jitter at the CLK0 output
All
CLKOUT_PER_JITT_90
Period jitter at the CLK90 output
CLKOUT_PER_JITT_180
Period jitter at the CLK180 output
CLKOUT_PER_JITT_270
Period jitter at the CLK270 output
CLKOUT_PER_JITT_2X
Period jitter at the CLK2X and CLK2X180 outputs
CLKOUT_PER_JITT_DV1
CLKOUT_PER_JITT_DV2
Period jitter at the CLKDV output when performing integer division
Period jitter at the CLKDV output when performing non-integer division
Duty Cycle⁽⁴⁾
CLKOUT_DUTY_CYCLE_DLL Duty cycle variation for the CLK0, CLK90, CLK180, CLK270, CLK2X,
All
CLK2X180, and CLKDV outputs, including the BUFGMUX and clock tree
duty-cycle distortion
Phase Alignment⁽⁴⁾
CLKIN_CLKFB_PHASE
Phase offset between the CLKIN and CLKFB inputs
All
CLKOUT_PHASE_DLL
Phase offset between DLL outputs
CLK0 to CLK2X
(not CLK2X180)
All others
Lock Time
LOCK_DLL⁽³⁾
Delay Lines
DCM_DELAY_STEP⁽⁵⁾
When using the DLL alone: The time from 5 MHz < F_CLKIN < 15 MHz
All
deassertion at the DCM’s Reset input to
the rising transition at its LOCKED
F_CLKIN > 15 MHz
output. When the DCM is locked, the
CLKIN and CLKFB signals are in phase
Finest delay resolution, averaged over all steps
All
Speed Grade
-4
Min
Max
Units
5
5
10
0.3125
250
MHz
200
MHz
334
MHz
166
MHz
-
±100
ps
-
±150
ps
-
±150
ps
-
±150
ps
-
±[0.5% of
ps
CLKIN period
+ 100]
-
±150
ps
-
±[0.5% of
ps
CLKIN period
+ 100]
-
±[1% of CLKIN ps
period + 350]
-
±150
ps
-
±[1% of CLKIN ps
period + 100]
-
±[1% of CLKIN ps
period + 150]
-
5
ms
-
600
μs
15
35
ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 37.
2. Indicates the maximum amount of output jitter that the DCM adds to the jitter on the CLKIN input.
3. For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
4. Some jitter and duty-cycle specifications include 1% of input clock period or 0.01 UI. For example, the data sheet specifies a maximum jitter of “±[1%
of CLKIN period + 150]”. Assume the CLKIN frequency is 100 MHz. The equivalent CLKIN period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps.
According to the data sheet, the maximum jitter is ±[100 ps + 150 ps] = ±250 ps, averaged over all steps.
5. The typical delay step size is 23 ps.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
39