DS705 Datasheet, PDF (15/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
External Termination Requirements for Differential I/O
LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
X-Ref Target - Figure 5
Bank 0 and 2
Bank 0
VCCO = 3.3V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
VCCO = 2.5V
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
Bank 2
Any Bank
Bank 0
1/4th of Bourns
Part Number
Z0 = 50Ω CAT16-PT4F4 ^{Bank 2}
Z0 = 50Ω
100Ω
No VCCO Restrictions
LVDS_33, LVDS_25,
MINI_LVDS_33,
MINI_LVDS_25,
RSDS_33, RSDS_25,
PPDS_33, PPDS_25
VCCO = 3.3V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
DIFF_TERM=No
a) Input-only differential pairs or pairs not using DIFF_TERM=Yes constraint
VCCO = 2.5V
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
Z0 = 50Ω
Z0 = 50Ω
R_DT
VCCO = 3.3V
LVDS_33,
MINI_LVDS_33,
RSDS_33,
PPDS_33
VCCO = 2.5V
LVDS_25,
MINI_LVDS_25,
RSDS_25,
PPDS_25
DIFF_TERM=Yes
b) Differential pairs using DIFF_TERM=Yes constraint
DS705_06_061908
Figure 5: External Input Termination for LVDS, RSDS, MINI_LVDS, and PPDS I/O Standards
BLVDS_25 I/O Standard
X-Ref Target - Figure 6
Any Bank
Bank 0
Bank 2
V_CCO = 2.5V
1/4th of Bourns
Part Number
CAT16-LV4F12
165Ω
Any Bank
Bank 0
1/4th of Bourns
Part Number
CAT16-PT4F4 _{Bank 2}
Z0 = 50Ω
No V_CCO Requirement
BLVDS_25
140Ω _{Z0 = 50Ω}
100Ω BLVDS_25
165Ω
DS705_07_061908
Figure 6: External Output and Input Termination Resistors for BLVDS_25 I/O Standard
TMDS_33 I/O Standard
X-Ref Target - Figure 7
Bank 0 and 2
Bank 0
Bank 2
VCCO = 3.3V
3.3V
Any Bank
Bank 0
50Ω
50Ω ^{Bank 2}
VCCAUX = 3.3V
TMDS_33
TMDS_33
DVI/HDMI cable
DS705_08_061908
Figure 7: External Input Resistors Required for TMDS_33 I/O Standard
Device DNA Read Endurance
Table 15: Device DNA Identifier Memory Characteristics
Symbol
Description
DNA_CYCLES
Number of READ operations or JTAG ISC_DNA read operations. Unaffected by
HOLD or SHIFT operations.
Minimum
30,000,000
Units
Read
cycles
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
15