DS705 Datasheet, PDF (12/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Table 12: DC Characteristics of User I/Os Using Single-
Ended Standards
IOSTANDARD
Attribute
LVTTL⁽³⁾
2
Test
Conditions
I_OL I_OH
(mA) (mA)
2 –2
Logic Level
Characteristics
V_OL
Max (V)
V_OH
Min (V)
0.4
2.4
4
4 –4
6
6 –6
8
8 –8
12 12 –12
16 16 –16
24 24⁽⁶⁾ –24
LVCMOS33⁽³⁾ 2
2 –2
4
4 –4
0.4
V_CCO – 0.4
6
6 –6
8
8 –8
12 12 –12
16
24⁽⁴⁾
16 –16⁽⁶⁾
24 –24⁽⁶⁾
LVCMOS25⁽³⁾ 2
2 –2
0.4
4
4 –4
V_CCO – 0.4
6
6 –6
8
8 –8
12
16⁽⁴⁾
12 –12
16 –16⁽⁶⁾
24⁽⁴⁾ 24⁽⁶⁾ –24⁽⁶⁾
LVCMOS18⁽³⁾ 2
2 –2
0.4
4
4 –4
6
6 –6⁽⁶⁾
V_CCO – 0.4
8
12⁽⁴⁾
8 –8
12 –12⁽⁶⁾
16⁽⁴⁾ 16 –16
LVCMOS15⁽³⁾ 2
2 –2
0.4
4
4 –4
V_CCO – 0.4
6
6 –6
8⁽⁴⁾
8
–8
12⁽⁴⁾ 12 –12
LVCMOS12⁽³⁾ 2
2 –2
4⁽⁴⁾
4
–4
0.4
V_CCO – 0.4
6⁽⁴⁾
6
–6
PCI33_3⁽⁵⁾
1.5 –0.5 10% V_CCO 90% V_CCO
Table 12: DC Characteristics of User I/Os Using Single-
Ended Standards (Cont’d)
IOSTANDARD
Attribute
HSTL_I⁽⁴⁾
HSTL_III⁽⁴⁾
HSTL_I_18
HSTL_II_18⁽⁴⁾
HSTL_III_18
SSTL18_I
SSTL18_II⁽⁴⁾
SSTL2_I
SSTL2_II⁽⁴⁾
SSTL3_I
SSTL3_II⁽⁴⁾
Test
Conditions
Logic Level
Characteristics
I_OL I_OH
V_OL
(mA) (mA) Max (V)
V_OH
Min (V)
8 –8
24⁽⁷⁾ –8
0.4
V_CCO - 0.4
0.4
V_CCO - 0.4
8 –8
0.4
V_CCO - 0.4
16 –16⁽⁷⁾
0.4
24⁽⁷⁾ –8
0.4
V_CCO - 0.4
V_CCO - 0.4
6.7 –6.7 V_TT – 0.475 V_TT + 0.475
13.4 –13.4 V_TT – 0.475 V_TT + 0.475
8.1 –8.1 V_TT – 0.61 V_TT + 0.61
16.2 –16.2 V_TT – 0.80 V_TT + 0.80
8
–8 V_TT – 0.6 V_TT + 0.6
16 –16 V_TT – 0.8 V_TT + 0.8
Notes:
1. The numbers in this table are based on the conditions set forth in
Table 8 and Table 11.
2. Descriptions of the symbols used in this table are as follows:
– I_OL the output current condition under which V_OL is tested
– I_OH the output current condition under which V_OH is tested
– V_OL the output voltage that indicates a Low logic level
– V_OH the output voltage that indicates a High logic level
– V_IL the input voltage that indicates a Low logic level
– V_IH the input voltage that indicates a High logic level
– V_CCO the supply voltage for output drivers
– V_REF the reference voltage for setting the input switching threshold
– V_TT the voltage applied to a resistor termination
3. For the LVCMOS and LVTTL standards: the same V_OL and V_OH
limits apply for both the Fast and Slow slew attributes.
4. These higher-drive output standards are supported only on FPGA
banks 1 and 3. Inputs are unrestricted. See the chapter “Using I/O
Resources” in UG331.
5. Tested according to the relevant PCI specifications. For
information on PCI IP solutions, see www.xilinx.com/pci. The PCI
IOSTANDARD is not supported on input-only pins.
6. Derate by 20% for T_J above 100°C.
7. Derate by 5% for T_J above 100°C.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
12