DS705 Datasheet, PDF (41/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Phase Shifter
Table 41: Recommended Operating Conditions for the PS in Variable Phase Mode
Symbol
Description
Operating Frequency Ranges
PSCLK_FREQ (F_PSCLK)
Frequency for the PSCLK input
Input Pulse Requirements
PSCLK_PULSE
PSCLK pulse width as a percentage of the PSCLK period
Speed Grade
-4
Min
Max
Units
1
167
MHz
40%
60%
-
Table 42: Switching Characteristics for the PS in Variable Phase Mode
Symbol
Description
Phase Shifting Range
MAX_STEPS⁽²⁾
Maximum allowed number of
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double
the clock effective clock period.
CLKIN < 60 MHz
CLKIN ≥ 60 MHz
FINE_SHIFT_RANGE_MIN Minimum guaranteed delay for variable phase shifting
FINE_SHIFT_RANGE_MAX Maximum guaranteed delay for variable phase shifting
Phase Shift Amount
±[INTEGER(10 • (T_CLKIN – 3 ns))]
±[INTEGER(15 • (T_CLKIN – 3 ns))]
±[MAX_STEPS •
DCM_DELAY_STEP_MIN]
±[MAX_STEPS •
DCM_DELAY_STEP_MAX]
Units
steps
ns
ns
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8 and Table 41.
2. The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
3. The DCM_DELAY_STEP values are provided at the bottom of Table 38.
Miscellaneous DCM Timing
Table 43: Miscellaneous DCM Timing
Symbol
DCM_RST_PW_MIN
Description
Minimum duration of a RST pulse width
Min
Max
Units
3
-
CLKIN
cycles
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
41