DS705 Datasheet, PDF (35/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Block RAM Timing
Table 34: Block RAM Timing
Symbol
Description
Clock-to-Output Times
T_{RCKO_DOA_NC} When reading from block RAM, the delay from the active transition at the CLK input to data
appearing at the DOUT output
T_{RCKO_DOA}
Clock CLK to DOUT output (with output register)
Setup Times
T_{RCCK_ADDR} Setup time for the ADDR inputs before the active transition at the CLK input of the block
RAM
T_{RDCK_DIB}
Setup time for data at the DIN inputs before the active transition at the CLK input of the
block RAM
T_{RCCK_ENB}
T_{RCCK_WEB}
T_{RCCK_REGCE}
T_{RCCK_RST}
Hold Times
Setup time for the EN input before the active transition at the CLK input of the block RAM
Setup time for the WE input before the active transition at the CLK input of the block RAM
Setup time for the CE input before the active transition at the CLK input of the block RAM
Setup time for the RST input before the active transition at the CLK input of the block RAM
T_{RCKC_ADDR}
T_{RDCK_DIB}
T_{RCKC_ENB}
T_{RCKC_WEB}
T_{RCKC_REGCE}
T_{RCKC_RST}
Clock Timing
Hold time on the ADDR inputs after the active transition at the CLK input
Hold time on the DIN inputs after the active transition at the CLK input
Hold time on the EN input after the active transition at the CLK input
Hold time on the WE input after the active transition at the CLK input
Hold time on the CE input after the active transition at the CLK input
Hold time on the RST input after the active transition at the CLK input
T_BPWH
High pulse width of the CLK signal
T_BPWL
Low pulse width of the CLK signal
Clock Frequency
F_BRAM
Block RAM clock frequency
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
Speed Grade
-4
Min Max
-
2.80
-
1.45
0.46
-
0.33
-
0.60
-
0.75
-
0.40
-
0.25
-
0.10
-
0.10
-
0.10
-
0.10
-
0.10
-
0.10
-
1.79
-
1.79
-
0
280
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
35