DS705 Datasheet, PDF (47/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Slave Serial Mode Timing
X-Ref Target - Figure 11
PROG_B
(Input)
INIT_B
(Open-Drain)
CCLK
(Input)
DIN
(Input)
DOUT
(Output)
T_DCC
T_CCD
Bit 0
Bit 1
T_MCCL
T_SCCL
T_MCCH
T_SCCH
1/F_CCSER
Bit n Bit n+1
T_CCO
Bit n-64 Bit n-63
Figure 11: Waveforms for Slave Serial Configuration
DS705_12_062308
Table 51: Timing for the Slave Serial Configuration Modes
Symbol
Description
Clock-to-Output Times
T_CCO
The time from the falling transition on the CCLK pin to data appearing at the DOUT pin
Setup Times
T_DCC
The time from the setup of data at the DIN pin to the rising transition at the CCLK pin
Hold Times
T_CCD
The time from the rising transition at the CCLK pin to the point when data is last held at
the DIN pin
Clock Timing
T_CCH
T_CCL
F_CCSER
High pulse width at the CCLK input pin
Low pulse width at the CCLK input pin
Frequency of the clock signal at the CCLK
input pin
No bitstream compression
With bitstream compression
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 8.
2. For serial configuration with a daisy-chain of multiple FPGAs, the maximum limit is 25 MHz.
Min
Max Units
1.5
10
ns
7
-
ns
1.0
-
ns
See Table 50
See Table 50
0
100
MHz
0
100
MHz
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
47