DS705 Datasheet, PDF (26/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation

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XA Spartan-3A DSP Automotive FPGA Family Data Sheet
Table 26: Output Timing Adjustments for IOB (Cont’d)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard (IOSTANDARD)
Differential Standards
LVDS_25
LVDS_33
BLVDS_25
MINI_LVDS_25
MINI_LVDS_33
LVPECL_25
LVPECL_33
RSDS_25
RSDS_33
TMDS_33
PPDS_25
PPDS_33
DIFF_HSTL_I_18
DIFF_HSTL_II_18
DIFF_HSTL_III_18
DIFF_HSTL_I
DIFF_HSTL_III
DIFF_SSTL18_I
DIFF_SSTL18_II
DIFF_SSTL2_I
DIFF_SSTL2_II
DIFF_SSTL3_I
DIFF_SSTL3_II
Add the
Adjustment
Below
Speed Grade
-4
Units
1.49
ns
0.46
ns
0.11
ns
1.11
ns
0.41
ns
Input Only
1.72
ns
0.64
ns
0.46
ns
1.28
ns
0.88
ns
0.43
ns
0.41
ns
0.36
ns
1.01
ns
1.16
ns
0.49
ns
0.41
ns
0.91
ns
0.10
ns
1.18
ns
0.28
ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 27 and are based on the operating
conditions set forth in Table 8, Table 11, and Table 13.
2. These adjustments are used to convert output- and three-state-
path times originally specified for the LVCMOS25 standard with
12 mA drive and Fast slew rate to times that correspond to other
signal standards. Do not adjust times that measure when
outputs go into a high-impedance state.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
26