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DS705 Datasheet, PDF (13/54 Pages) Xilinx, Inc – Integrated adder for complex multiply or multiply-add operation
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Differential I/O Standards
X-Ref Target - Figure 3
Internal
Logic
XA Spartan-3A DSP Automotive FPGA Family Data Sheet
VINP
P
Differential
VINN
N
I/O Pair Pins
VINN
VINP
50%
VID
VICM
GND level
VICM
=
Input
common
mode
voltage
=
VINP
+
2
VINN
VID = Differential input voltage = VINP - VINN
DS705_04_061908
Figure 3: Differential Input Voltages
Table 13: Recommended Operating Conditions for User I/Os Using Differential Signal Standards
IOSTANDARD Attribute
VCCO for Drivers(1)
VID
Min (V) Nom (V) Max (V) Min (mV) Nom (mV) Max (mV) Min (V)
VICM(2)
Nom (V)
Max (V)
LVDS_25(3)
LVDS_33(3)
BLVDS_25(4)
2.25
2.5
2.75
100
350
600
0.3
1.25
2.35
3.0
3.3
3.6
100
350
600
0.3
1.25
2.35
2.25
2.5
2.75
100
300
–
0.3
1.3
2.35
MINI_LVDS_25(3)
2.25
2.5
2.75
200
–
600
0.3
1.2
1.95
MINI_LVDS_33(3)
3.0
3.3
3.6
200
–
600
0.3
1.2
1.95
LVPECL_25(5)
LVPECL_33(5)
RSDS_25(3)
Inputs Only
100
Inputs Only
100
2.25
2.5
2.75
100
800
1000
0.3
800
1000
0.3
200
–
0.3
1.2
1.95
1.2
2.8(6)
1.2
1.5
RSDS_33(3)
3.0
3.3
3.6
100
200
–
0.3
1.2
1.5
TMDS_33(3,4,7)
3.14
3.3
3.47
150
–
1200
2.7
–
3.23
PPDS_25(3)
2.25
2.5
2.75
100
–
400
0.2
–
2.3
PPDS_33(3)
3.0
3.3
3.6
100
–
400
0.2
–
2.3
DIFF_HSTL_I_18
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_II_18(8)
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_III_18
1.7
1.8
1.9
100
–
–
0.8
–
1.1
DIFF_HSTL_I
1.4
1.5
1.6
100
–
–
0.68
–
0.9
DIFF_HSTL_III
1.4
1.5
1.6
100
–
–
–
0.9
–
DIFF_SSTL18_I
DIFF_SSTL18_II(8)
1.7
1.8
1.9
100
–
1.7
1.8
1.9
100
–
–
0.7
–
1.1
–
0.7
–
1.1
DIFF_SSTL2_I
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL2_II(8)
2.3
2.5
2.7
100
–
–
1.0
–
1.5
DIFF_SSTL3_I
3.0
3.3
3.6
100
–
–
1.1
–
1.9
DIFF_SSTL3_II
3.0
3.3
3.6
100
–
–
1.1
–
1.9
Notes:
1. The VCCO rails supply only differential output drivers, not input circuits.
2. VICM must be less than VCCAUX.
3. These true differential output standards are supported only on FPGA banks 0 and 2. Inputs are unrestricted. See the chapter “Using I/O Resources” in UG331.
4. See "External Termination Requirements for Differential I/O."
5. LVPECL is supported on inputs only, not outputs. Requires VCCAUX = 3.3V ± 10%.
6. LVPECL_33 maximum VICM = VCCAUX – (VID/2).
7. Requires VCCAUX = 3.3V ± 10%. (VCCAUX - 300 mV) ≤ VICM ≤ (VCCAUX - 37 mV).
8. These higher-drive output standards are supported only on FPGA banks 1 and 3. Inputs are unrestricted. See the chapter “Using I/O Resources” in UG331.
9. VREF inputs are used for the DIFF_SSTL and DIFF_HSTL standards. The VREF settings are the same as for the single-ended versions in Table 11. Other differential
standards do not use VREF.
DS705 (v1.1) January 20, 2009
www.xilinx.com
Product Specification
13
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