MSP430FR6889 Datasheet, PDF (90/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
www.ti.com
6.11.23 Input/Output Schematics
6.11.23.1 Digital I/O Functionality Port P1, P2, P3, P4, P5, P6, P7, P8, P9, and P10
The port pins provide the following features:
• Interrupt and wakeup from LPMx.5 capability for ports P1, P2, P3, and P4
• Capacitive touch functionality (see Section 6.11.23.2)
• Up to three digital module input or output functions
• LCD segment functionality (not all pins, package dependent)
Figure 6-1 shows the features and the corresponding control logic (not including the capacitive touch
logic). It is applicable for all port pins P1.0 through P10.2 unless a dedicated schematic is available in the
following sections. The module functions provided per pin and whether the direction is controlled by the
module or by the port direction register for the selected secondary function are described in the pin
function tables.
Sz
LCDSz
PxREN.y
PxDIR.y
00
From module 1^(B)
01
From module 2^(B)
10
From module 3^(B)
11
Pad Logic
Direction
0: Input
1: Output
DVSS
0
DVCC
1
1
PxOUT.y
00
From module 1
01
From module 2
10
From module 3
11
PxSEL1.y
PxSEL0.y
PxIN.y
Px.y/Mod1/Mod2/Mod3/Sz
To module 1^(A)
To module 2^(A)
To module 3^(A)
A. The inputs from several pins toward a module are ORed together.
B. The direction is controlled either by the connected module or by the corresponding PxDIR.y bit. Refer to the pin
function tables.
NOTE: Functional representation only.
Figure 6-1. General Port Pin Schematic
90
Detailed Description
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