MSP430FR6889 Datasheet, PDF (22/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
www.ti.com
Table 4-2. MSP430FR588x, MSP430FR588x1 Signal Descriptions (continued)
TERMINAL
NAME
P3.0/UCB1CLK
PM
RGC
NO.
14
DESCRIPTION
General-purpose digital I/O
USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI master mode)
General-purpose digital I/O
P3.1/UCB1SIMO/UCB1SDA
15 USCI_B1: Slave in, master out (SPI mode)
USCI_B1: I²C data (I²C mode)
General-purpose digital I/O
P3.2/UCB1SOMI/UCB1SCL
DVSS1
DVCC1
TEST/SBWTCK
RST/NMI/SBWTDIO
16 USCI_B1: Slave out, master in (SPI mode)
USCI_B1: I²C clock (I²C mode)
17 Digital ground supply
18 Digital power supply
Test mode pin - select digital I/O on JTAG pins
19
Spy-Bi-Wire input clock
Reset input active low; Nonmaskable interrupt input
20
Spy-Bi-Wire data input/output
General-purpose digital I/O
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1
Test data output port
21 Switch all PWM outputs high impedance input - Timer_B TB0
SMCLK output
Low-power debug: CPU Status register SCG1
General-purpose digital I/O
PJ.1/TDI/TCLK/MCLK/SRSCG0
Test data input or test clock input
22
MCLK output
Low-power debug: CPU Status register SCG0
General-purpose digital I/O
PJ.2/TMS/ACLK/SROSCOFF
Test mode select
23
ACLK output (divided by 1, 2, 4, or 8)
Low-power debug: CPU Status register OSCOFF
General-purpose digital I/O
PJ.3/TCK/COUT/SRCPUOFF
Test clock
24
Comparator output
Low-power debug: CPU Status register CPUOFF
General-purpose digital I/O
P3.3/TA1.1/TB0CLK
25 Timer_A TA1 CCR1 capture: CCI1A input, compare: Out1 output
Timer_B TB0 clock signal TB0CLK input
General-purpose digital I/O
P3.4/UCA1SIMO/UCA1TXD/TB0.0
USCI_A1: Slave in, master out (SPI mode)
26
USCI_A1: Transmit data (UART mode)
Timer_B TB0 CCR0 capture: CCI0A input, compare: Out0 output
22
Terminal Configuration and Functions
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MSP430FR58891 MSP430FR5888 MSP430FR5887