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MSP430FR6889 Datasheet, PDF (68/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
www.ti.com
Table 5-39. Extended Scan Interface, 12-Bit DAC
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
ESIDVCC = AVCC = DVCC
VCC
ESI DAC supply voltage
(connected together),
ESIDVSS = AVSS = DVSS
(connected together)
ICC
ESI 12-bit DAC operating supply
current into AVCC terminal (1)
2.2 V
3V
Resolution
INL
Integral nonlinearity
RL = 1000 MΩ, CL = 20 pF
With autozeroing
2.2 V, 3 V
DNL
Differential nonlinearity
RL = 1000 MΩ, CL = 20 pF,
Without autozeroing
RL = 1000 MΩ, CL = 20 pF,
With autozeroing
2.2 V, 3 V
2.2 V, 3 V
EOS
EG
ton(ESIDAC)
Offset error
Gain error
On time after AVCC of ESIDAC is
switched on
With autozeroing
With autozeroing
V+ESICA - VESIDAC = ±6 mV
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
tSettle(ESIDAC)
Settling time
ESIDAC code = 0h → A0h
ESIDAC code = A0h → 0h
2.2 V, 3 V
2.2 V, 3 V
(1) This parameter covers one ESI 12-bit DAC, either ESI AFE1 12-bit DAC or ESI AFE2 12-bit DAC.
MIN TYP MAX UNIT
2.2
3.6 V
10
27
µA
14
35
12
bit
-10
±2 +10 LSB
-10
+10 LSB
-10
+10 LSB
0
V
0.6%
2 µs
2
µs
2
Table 5-40. Extended Scan Interface, Comparator
over operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP MAX UNIT
ESIDVCC = AVCC = DVCC
VCC
ESI comparator supply voltage
(connected together),
ESIDVSS = AVSS = DVSS
(connected together)
2.2
3.6 V
ICC
ESI comparator operating supply
current into AVCC terminal (1)
2.2 V, 3 V
25
42 µA
VIC
Common mode input voltage
range (2)
2.2 V, 3 V
0
VCC -
1V
V
VOffset
dVOffset/dT
Input offset voltage
Temperature coefficient of VOffset
(3)
After autozeroing
Without autozeroing
After autozeroing
2.2 V, 3 V -1.5
2.2 V, 3 V
1.5 mV
40
µV/°C
2
dVOffset/dVCC
VOffset supply voltage (VCC)
sensitivity (4)
Without autozeroing
After autozeroing
0.3
mV/V
0.2
Vhys
ton(ESICA)
tSettle(ESICA)
tautozero
Input voltage hysteresis
On time after ESICA is switched
on
Settle time
Autozeroing time of comparator
V+ terminal = V- terminal = 0.5 × VCC
V+ESICA - VESIDAC = +6 mV,
V+ESICA = 0.5 x AVCC
V+ESICA - VESIDAC = -12 mV → 6 mV,
V+ESICA = 0.5 x AVCC
Vinput = Vcc / 2
|Voffset| < 1 mV
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
2.2 V, 3 V
0.5
LSB
2.0 µs
3.0 µs
3.0 µs
(1) This parameter covers one single ESI comparator; either ESI AFE1 comparator or ESI AFE2 comparator.
(2) The comparator output is reliable when at least one of the input signals is within the common mode input voltage range.
(3) Calculated using the box method: (MAX(–40°C to 85°C) – MIN(–40°C to 85°C)) / MIN(–40°C to 85°C) / (85°C – (–40°C))
(4) Calculated using the box method: ABS((Voffset_Vcc_max – Voffset_Vcc_min)/(Vcc_max – Vcc_min))
68
Specifications
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