MSP430FR6889 Datasheet, PDF (13/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
Table 4-1. MSP430FR688x, MSP430FR688x1 Signal Descriptions (continued)
NAME
TERMINAL
PZ
NO. Seg.
PN
NO. Seg.
DESCRIPTION
General-purpose digital I/O
P5.1/TA1.2/Sx
20 S37
Timer_A TA1 CCR2 capture: CCI2A input, compare: Out2 output
LCD segment output (segment number is package specific)
General-purpose digital I/O
Timer_A TA1 CCR0 capture: CCI0B input, compare: Out0 output
P5.2/TA1.0/TA1CLK/ACLK/Sx 21 S36
Timer_A TA1 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, or 8)
LCD segment output (segment number is package specific)
General-purpose digital I/O
P5.3/UCB1STE/Sx
22 S35
USCI_B1: Slave transmit enable (SPI mode)
LCD segment output (segment number is package specific)
General-purpose digital I/O
P3.0/UCB1CLK/Sx
23
S34
18
S29
USCI_B1: Clock signal input (SPI slave mode), Clock signal output (SPI
master mode)
LCD segment output (segment number is package specific)
General-purpose digital I/O
P3.1/UCB1SIMO/UCB1SDA/
Sx
USCI_B1: Slave in, master out (SPI mode)
24 S33 19 S28
USCI_B1: I²C data (I²C mode)
LCD segment output (segment number is package specific)
General-purpose digital I/O
P3.2/UCB1SOMI/UCB1SCL/
Sx
USCI_B1: Slave out, master in (SPI mode)
25 S32 20 S27
USCI_B1: I²C clock (I²C mode)
DVSS1
DVCC1
TEST/SBWTCK
LCD segment output (segment number is package specific)
26
21
Digital ground supply
27
22
Digital power supply
Test mode pin - select digital I/O on JTAG pins
28
23
Spy-Bi-Wire input clock
Reset input active low
RST/NMI/SBWTDIO
29
24
Nonmaskable interrupt input
Spy-Bi-Wire data input/output
General-purpose digital I/O
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1
30
Test data output port
25
Switch all PWM outputs high impedance input - Timer_B TB0
SMCLK output
Low-power debug: CPU Status register SCG1
General-purpose digital I/O
PJ.1/TDI/TCLK/MCLK/
SRSCG0
31
Test data input or test clock input
26
MCLK output
Low-power debug: CPU Status register SCG0
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Terminal Configuration and Functions
13
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MSP430FR58891 MSP430FR5888 MSP430FR5887