MSP430FR6889 Datasheet, PDF (29/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
5.4 Active Mode Supply Current Into V_CC Excluding External Current (Havok)
over recommended operating free-air temperature (unless otherwise noted)^{(1) (2)}
PARAMETER
EXECUTION
MEMORY
FREQUENCY (f_MCLK = f_SMCLK)
1 MHz
4 MHz
8 MHz
12 MHz
16 MHz
V_CC
0 wait states
0 wait states
0 wait states
1 wait states
1 wait states UNIT
(NWAITSx = 0) (NWAITSx = 0) (NWAITSx = 0) (NWAITSx = 1) (NWAITSx = 1)
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
I_{AM, FRAM_UNI}
(Unified memory)⁽³⁾
FRAM
3.0 V
210
640
1220
1475
1845
µA
FRAM
I_{AM, FRAM}(0%) ^{(4) (5)}
0% cache hit 3.0 V
375
1290
2525
2100
2675
µA
ratio
I_{AM, FRAM}(50%)^{(4) (5)}
FRAM
50% cache hit 3.0 V
240
ratio
745
1440
1575
1990
µA
I_{AM, FRAM}(66%)^{(4) (5)}
FRAM
66% cache hit 3.0 V
200
ratio
560
1070
1300
1620
µA
I_{AM, FRAM}(75%)^{(4) (5)}
FRAM
75% cache hit
ratio
3.0 V
170 255 480
890 1085 1155 1310 1420 1620 µA
FRAM
I_{AM, FRAM}(100%^{(4) (5)}
100% cache hit 3.0 V
110
235
420
640
730
µA
ratio
I_{AM, RAM} ^{(6) (5)}
I_{AM, RAM only} ^{(7) (5)}
RAM
3.0 V
130
320
585
890
1070
µA
RAM
3.0 V
100 180 290
555
860
1040 1300 µA
(1) All inputs are tied to 0 V or to V_CC. Outputs do not source or sink any current.
(2) Characterized with program executing typical data processing.
f_ACLK = 32768 Hz, f_MCLK = f_SMCLK = f_DCO at specified frequency, except for 12 MHz. For 12 MHz, f_DCO = 24 MHz and
f_MCLK = f_SMCLK = f_DCO/2.
At MCLK frequencies above 8 MHz, the FRAM requires wait states. When wait states are required, the effective MCLK frequency
(f_MCLK,eff) decreases. The effective MCLK frequency also depends on the cache hit ratio. SMCLK is not affected by the number of wait
states or the cache hit ratio.
The following equation can be used to compute f_MCLK,eff:
f_MCLK,eff = f_MCLK / [wait states × (1 – cache hit ratio) + 1]
For example, with 1 wait state and 75% cache hit ratio f_MCKL,eff = f_MCLK / [1 × (1 – 0.75) + 1] = f_MCLK / 1.25.
(3) Represents typical program execution. Program and data reside entirely in FRAM. All execution is from FRAM.
(4) Program resides in FRAM. Data resides in SRAM. Average current dissipation varies with cache hit-to-miss ratio as specified. Cache hit
ratio represents number cache accesses divided by the total number of FRAM accesses. For example, a 75% ratio implies three of
every four accesses is from cache, and the remaining are FRAM accesses.
(5) See Figure 5-1 for typical curves. Each characteristic equation shown in the graph is computed using the least squares method for best
linear fit using the typical data shown in Section 5.4.
(6) Program and data reside entirely in RAM. All execution is from RAM.
(7) Program and data reside entirely in RAM. All execution is from RAM. FRAM is off.
Copyright © 2014–2015, Texas Instruments Incorporated
Specifications
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