MSP430FR6889 Datasheet, PDF (27/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
4.5 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for
example, if the device is in test mode). For details of the settings for each pin and schematics of the
multiplexed ports, see Section 6.11.23.
4.6 Connection of Unused Pins
The correct termination of all unused pins is listed in Table 4-3.
PIN
AVCC
AVSS
Px.0 to Px.7
R33/LCDCAP
ESIDVCC
ESIDVSS
ESICOM
ESICI
RST/NMI
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK
TEST
Table 4-3. Connection of Unused Pins⁽¹⁾
POTENTIAL
DV_CC
DV_SS
Open
DV_SS or DV_CC
DV_CC
DV_SS
Open
Open
DV_CC or V_CC
COMMENT
Switched to port function, output direction (PxDIR.n = 1)
If not used the pin can be tied to either supplies.
47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF⁽²⁾)
pulldown
Open
The JTAG pins are shared with general-purpose I/O function (PJ.x). If
not being used, these should be switched to port function, output
direction. When used as JTAG pins, these pins should remain open.
Open
This pin always has an internal pulldown enabled.
(1) Any unused pin with a secondary function that is shared with general-purpose I/O should follow the
Px.0 to Px.7 unused pin connection guidelines.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in
Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
Copyright © 2014–2015, Texas Instruments Incorporated
Terminal Configuration and Functions
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