MSP430FR6889 Datasheet, PDF (10/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
4.3 Pin Diagram – PM or RGC Package – MSP430FR588x, MSP430FR588x1
Figure 4-3 shows the 64-pin PM or RGC package pin assignments.
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P4.3/UCA0SOMI/UCA0RXD/UCB1STE
P1.4/UCB0CLK/UCA0STE/TA1.0
P1.5/UCB0STE/UCA0CLK/TA0.0
P1.6/UCB0SIMO/UCB0SDA/TA0.1
P1.7/UCB0SOMI/UCB0SCL/TA0.2
P2.4/TB0.3
P2.5/TB0.4
P2.6/TB0.5/ESIC1OUT
P2.7/TB0.6/ESIC2OUT
P5.0/TA1.1/MCLK
P5.1/TA1.2
P5.2/TA1.0/TA1CLK/ACLK
P5.3/UCB1STE
P3.0/UCB1CLK
P3.1/UCB1SIMO/UCB1SDA
P3.2/UCB1SOMI/UCB1SCL
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
1
48
2
47
3
46
4
45
5
44
6
43
7
42
8
41
9
40
10
39
11
38
12
37
13
36
14
35
15
34
16
33
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
ESIDVCC
P9.7/ESICI3/A15/C15
P9.6/ESICI2/A14/C14
P9.5/ESICI1/A13/C13
P9.4/ESICI0/A12/C12
P9.3/ESICH3/ESITEST3/A11/C11
P9.2/ESICH2/ESITEST2/A10/C10
P9.1/ESICH1/ESITEST1/A9/C9
P9.0/ESICH0/ESITEST0/A8/C8
P1.0/TA0.1/DMAE0/RTCCLK/A0/C0/VREF-/VeREF-
P1.1/TA0.2/TA1CLK/COUT/A1/C1/VREF+/VeREF+
P1.2/TA1.1/TA0CLK/COUT/A2/C2
P1.3/TA1.2/ESITEST4/A3/C3
DVCC2
DVSS2
P2.0/UCA0SIMO/UCA0TXD/TB0.6/TB0CLK
On devices with UART BSL: P2.0: BSLTX; P2.1: BSLRX
On devices with I²C BSL: P1.6: BSLSDA; P1.7: BSLSCL
Figure 4-3. 64-Pin PM or RGC Package (Top View)
10
Terminal Configuration and Functions
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Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887