MSP430FR6889 Datasheet, PDF (78/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
www.ti.com
Table 6-6. Spy-Bi-Wire Pin Requirements and Functions
DEVICE SIGNAL
TEST/SBWTCK
RST/NMI/SBWTDIO
VCC
VSS
DIRECTION
IN
IN, OUT
FUNCTION
Spy-Bi-Wire clock input
Spy-Bi-Wire data input/output
Power supply
Ground supply
6.7 FRAM
The FRAM can be programmed via the JTAG port, Spy-Bi-Wire (SBW), the BSL, or in-system by the CPU.
Features of the FRAM include:
• Ultra-low-power ultra-fast write nonvolatile memory
• Byte and word access capability
• Programmable wait state generation
• Error correction coding (ECC)
Wait States
NOTE
For MCLK frequencies > 8 MHz, wait states must be configured following the flow
described in the "FRAM Controller (FRCTRL)" chapter, section "Wait State Control"
of the MSP430FR58xx, MSP430FR59xx, MSP430FR68xx, MSP430FR69xx Family
User's Guide (SLAU367).
For important software design information regarding FRAM including but not limited to partitioning the
memory layout according to application-specific code, constant, and data space requirements, the use of
FRAM to optimize application energy consumption, and the use of the memory protection unit (MPU) to
maximize application robustness by protecting the program code against unintended write accesses, see
the application report MSP430™ FRAM Technology – How To and Best Practices (SLAA628).
6.8 RAM
The RAM is made up of one sector. The sector can be completely powered down in LPM3 and LPM4 to
save leakage; however, all data is lost during shutdown.
6.9 Tiny RAM
The Tiny RAM can be used to hold data or a very small stack if the complete RAM is powered down in
LPM3 and LPM4.
6.10 Memory Protection Unit Including IP Encapsulation
The FRAM can be protected from inadvertent CPU execution, read or write access by the MPU. Features
of the MPU include:
• IP Encapsulation with programmable boundaries (prevents reads from "outside" like JTAG or non-IP
software) in steps of 1KB.
• Main memory partitioning programmable up to three segments in steps of 1KB.
• The access rights of each segment (main and information memory) can be individually selected.
• Access violation flags with interrupt capability for easy servicing of access violations.
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Detailed Description
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