MSP430FR6889 Datasheet, PDF (7/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

www.ti.com
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
3 Device Comparison
Table 3-1 and Table 3-2 summarize the available family members.
Table 3-1. Device Comparison (With UART BSL)^{(1) (2)}
DEVICE
MSP430FR6889
MSP430FR6888
MSP430FR6887
MSP430FR5889
MSP430FR5888
MSP430FR5887
FRAM
(KB)
128
96
64
128
96
64
SRAM
(KB)
2
2
2
2
2
2
CLOCK
SYSTEM
DCO
HFXT
LFXT
DCO
HFXT
LFXT
DCO
HFXT
LFXT
DCO
HFXT
LFXT
DCO
HFXT
LFXT
DCO
HFXT
LFXT
Timer_A
(3)
3, 3 ⁽⁷⁾
2, 5 ⁽⁸⁾
3, 3 ⁽⁷⁾
2, 5 ⁽⁸⁾
3, 3 ⁽⁷⁾
2, 5 ⁽⁸⁾
3, 3 ⁽⁷⁾
2, 5 ⁽⁸⁾
3, 3 ⁽⁷⁾
2, 5 ⁽⁸⁾
3, 3 ⁽⁷⁾
2, 5 ⁽⁸⁾
Timer_B
(4)
7
7
7
7
7
7
eUSCI
A ⁽⁵⁾
B ⁽⁶⁾
2
2
2
2
2
2
2
2
2
2
2
2
AES
no
no
no
no
no
no
ADC12_B LCD_C
12 ext
16 ext
12 ext
16 ext
12 ext
16 ext
240 seg
320 seg
240 seg
320 seg
240 seg
320 seg
12 ext
N/A
12 ext
N/A
12 ext
N/A
I/O
PACKAGE
TYPE
63
80 PN
83
100 PZ
63
80 PN
83
100 PZ
63
80 PN
83
100 PZ
48
64 PM
64 RGC
48
64 PM
64 RGC
48
64 PM
64 RGC
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/package.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(6) eUSCI_B supports I²C with multiple slave addresses and SPI.
(7) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(8) Timer_A TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).
Table 3-2. Device Comparison (With I²C BSL) ^{(1) (2)}
DEVICE
FRAM
(KB)
SRAM CLOCK Timer_A Timer_B
(KB) SYSTEM
(3)
(4)
eUSCI
A ⁽⁵⁾
B ⁽⁶⁾
AES ADC12_B LCD_C
I/O
PACKAGE
TYPE
MSP430FR68891
128
2
DCO
HFXT
LFXT
3, 3 ⁽⁷⁾
2, 5 ⁽⁸⁾
7
2
2
no
12 ext 240 seg 63
16 ext 320 seg 83
80 PN
100 PZ
MSP430FR58891
128
2
DCO
HFXT
LFXT
3, 3 ⁽⁷⁾
2, 5 ⁽⁸⁾
7
2
2
no
12 ext
N/A
48
64 PM
64 RGC
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/package.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 and the second instantiation having 5 capture compare registers and PWM output generators, respectively.
(5) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(6) eUSCI_B supports I²C with multiple slave addresses and SPI.
(7) Timer_A TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(8) Timer_A TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any).
Copyright © 2014–2015, Texas Instruments Incorporated
Device Comparison
7
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MSP430FR58891 MSP430FR5888 MSP430FR5887