MSP430FR6889 Datasheet, PDF (82/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
www.ti.com
6.11.8 DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC10_B conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode, without
having to awaken to move data to or from a peripheral.
Table 6-9. DMA Trigger Assignments⁽¹⁾
Trigger
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Channel 0
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2 CCR0 CCIFG
TA3 CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
Reserved
Reserved
Reserved
Reserved
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I²C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I²C)
UCB0RXIFG1 (I²C)
UCB0TXIFG1 (I²C)
UCB0RXIFG2 (I²C)
UCB0TXIFG2 (I²C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I²C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I²C)
Channel 1
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2 CCR0 CCIFG
TA3 CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
Reserved
Reserved
Reserved
Reserved
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I²C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I²C)
UCB0RXIFG1 (I²C)
UCB0TXIFG1 (I²C)
UCB0RXIFG2 (I²C)
UCB0TXIFG2 (I²C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I²C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I²C)
26
ADC12 end of conversion ADC12 end of conversion
27
Reserved
28
ESI
29
MPY ready
30
DMA2IFG
31
DMAE0
Reserved
ESI
MPY ready
DMA0IFG
DMAE0
(1) If a reserved trigger source is selected, no trigger is generated.
Channel 2
DMAREQ
TA0CCR0 CCIFG
TA0CCR2 CCIFG
TA1CCR0 CCIFG
TA1CCR2 CCIFG
TA2 CCR0 CCIFG
TA3 CCR0 CCIFG
TB0CCR0 CCIFG
TB0CCR2 CCIFG
Reserved
Reserved
Reserved
Reserved
Reserved
UCA0RXIFG
UCA0TXIFG
UCA1RXIFG
UCA1TXIFG
UCB0RXIFG (SPI)
UCB0RXIFG0 (I²C)
UCB0TXIFG (SPI)
UCB0TXIFG0 (I²C)
UCB0RXIFG1 (I²C)
UCB0TXIFG1 (I²C)
UCB0RXIFG2 (I²C)
UCB0TXIFG2 (I²C)
UCB1RXIFG (SPI)
UCB1RXIFG0 (I²C)
UCB1TXIFG (SPI)
UCB1TXIFG0 (I²C)
ADC12 end of
conversion
Reserved
ESI
MPY ready
DMA1IFG
DMAE0
82
Detailed Description
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