MSP430FR6889 Datasheet, PDF (51/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
5.13.5.3 eUSCI
f_eUSCI
f_BITCLK
Table 5-16. eUSCI (UART Mode) Recommended Operating Conditions
PARAMETER
eUSCI input clock frequency
BITCLK clock frequency
(equals baud rate in MBaud)
CONDITIONS
Internal: SMCLK, ACLK
External: UCLK
Duty cycle = 50% ± 10%
V_CC
MIN TYP
MAX UNIT
16 MHz
4 MHz
Table 5-17. eUSCI (UART Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
UCGLITx = 0
V_CC
MIN TYP MAX UNIT
5
30
t_t
UART receive deglitch time⁽¹⁾
UCGLITx = 1
UCGLITx = 2
2.2 V,
20
3.0 V
35
90
ns
160
UCGLITx = 3
50
220
(1) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. Thus the selected deglitch
time can limit the max. useable baud rate. To ensure that pulses are correctly recognized their width should exceed the maximum
specification of the deglitch time.
f_eUSCI
Table 5-18. eUSCI (SPI Master Mode) Recommended Operating Conditions
PARAMETER
eUSCI input clock frequency
CONDITIONS
Internal: SMCLK, ACLK
Duty cycle = 50% ± 10%
V_CC
MIN TYP
MAX UNIT
16 MHz
Table 5-19. eUSCI (SPI Master Mode)
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)⁽¹⁾
PARAMETER
TEST CONDITIONS
V_CC
MIN TYP MAX UNIT
t_STE,LEAD
t_STE,LAG
STE lead time, STE active to clock
STE lag time, Last clock to STE
inactive
UCSTEM = 1, UCMODEx = 01 or 10
UCSTEM = 1, UCMODEx = 01 or 10
1
UCxCL
K
1
cycles
t_STE,ACC
STE access time, STE active to
SIMO data out
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
60 ns
t_STE,DIS
STE disable time, STE inactive to
SOMI high impedance
UCSTEM = 0, UCMODEx = 01 or 10
2.2 V,
3.0 V
80 ns
t_SU,MI
SOMI input data setup time
2.2 V
40
ns
3.0 V
40
t_HD,MI
SOMI input data hold time
2.2 V
0
ns
3.0 V
0
t_VALID,MO SIMO output data valid time⁽²⁾
UCLK edge to SIMO valid,
C_L = 20 pF
2.2 V
3.0 V
10
ns
10
t_HD,MO
SIMO output data hold time⁽³⁾
C_L = 20 pF
2.2 V
3.0 V
0
ns
0
(1) f_UCxCLK = 1/2t_LO/HI with tL_O/HI = max(t_{VALID,MO(eUSCI)} + t_SU,SI(Slave), t_SU,MI(eUSCI) + t_{VALID,SO(Slave)}).
For the slave parameters t_SU,SI(Slave) and t_{VALID,SO(Slave)}, refer to the SPI parameters of the attached slave.
(2) Specifies the time to drive the next valid data to the SIMO output after the output changing UCLK clock edge. Refer to the timing
diagrams in Figure 5-15 and Figure 5-16.
(3) Specifies how long data on the SIMO output is valid after the output changing UCLK clock edge. Negative values indicate that the data
on the SIMO output can become invalid before the output changing clock edge observed on UCLK. Refer to the timing diagrams in
Figure 5-15 and Figure 5-16.
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Specifications
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