MSP430FR6889 Datasheet, PDF (125/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

www.ti.com
MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
Table 6-39. Port PJ (PJ.0 to PJ.3) Pin Functions
PIN NAME (PJ.x)
PJ.0/TDO/TB0OUTH/
SMCLK/SRSCG1
x
FUNCTION
0 PJ.0 (I/O) ⁽²⁾
TDO ⁽³⁾
TB0OUTH
SMCLK ⁽⁴⁾
N/A
CPU Status Register Bit SCG1
N/A
Internally tied to DVSS
CONTROL BITS/ SIGNALS ⁽¹⁾
PJDIR.x PJSEL1.x PJSEL0.x
I: 0; O: 1
0
0
X
X
X
0
0
1
1
0
1
0
1
0
1
1
1
PJ.1/TDI/TCLK/MCLK/
SRSCG0
1 PJ.1 (I/O) ⁽²⁾
TDI/TCLK ^{(3) (5)}
N/A
MCLK
N/A
CPU Status Register Bit SCG0
N/A
Internally tied to DVSS
I: 0; O: 1
0
0
X
X
X
0
0
1
1
0
1
0
1
0
1
1
1
PJ.2/TMS/ACLK/
SROSCOFF
2 PJ.2 (I/O) ⁽²⁾
TMS ^{(3) (5)}
N/A
ACLK
N/A
CPU Status Register Bit OSCOFF
N/A
Internally tied to DVSS
I: 0; O: 1
0
0
X
X
X
0
0
1
1
0
1
0
1
0
1
1
1
PJ.3/TCK/COUT/
SRCPUOFF
3 PJ.3 (I/O) ⁽²⁾
TCK ^{(3) (5)}
I: 0; O: 1
0
0
X
X
X
N/A
COUT
0
0
1
1
N/A
CPU Status Register Bit CPUOFF
0
1
0
1
N/A
Internally tied to DVSS
0
1
1
1
(1) X = Don't care
(2) Default condition
(3) The pin direction is controlled by the JTAG module. JTAG mode selection is made via the SYS module or by the SpyBiWire four wire
entry sequence. Neither PJSEL1.x and PJSEL0.x nor CEPD.x bits have an effect in these cases.
(4) NOTE: Do not use this pin as SMCLK output if the TB0OUTH functionality is used on any other pin. Select an alternative SMCLK output
pin.
(5) In JTAG mode, pullups are activated automatically on TMS, TCK, and TDI/TCLK. PJREN.x are do not care.
Copyright © 2014–2015, Texas Instruments Incorporated
Detailed Description 125
Submit Documentation Feedback
Product Folder Links: MSP430FR6889 MSP430FR68891 MSP430FR6888 MSP430FR6887 MSP430FR5889
MSP430FR58891 MSP430FR5888 MSP430FR5887