MSP430FR6889 Datasheet, PDF (79/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

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MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
6.11 Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using
all instructions. For complete module descriptions, see the MSP430FR58xx, MSP430FR59xx,
MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367).
6.11.1 Digital I/O
Up to eleven 8-bit I/O ports are implemented:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Programmable pullup or pulldown on all ports.
• Edge-selectable interrupt and LPM3.5 and LPM4.5 wakeup input capability is available for all pins of
ports P1, P2, P3, and P4.
• Read/write access to port-control registers is supported by all instructions.
• Ports can be accessed byte-wise or word-wise in pairs.
• Capacitive Touch functionality is supported on all pins of ports P1, P2, P3, P4, P5, P6, P7, P8, P9,
P10, and PJ.
• No cross-currents during start-up.
NOTE
Configuration of Digital I/Os After BOR Reset
To prevent any cross-currents during start-up of the device all port pins are high-
impedance with Schmitt triggers and their module functions disabled. To enable the
I/O functionality after a BOR reset the ports must be configured first and then the
LOCKLPM5 bit must be cleared. For details refer to the "Digital I/O" chapter,
section "Configuration After Reset" in the MSP430FR58xx, MSP430FR59xx,
MSP430FR68xx, MSP430FR69xx Family User's Guide (SLAU367).
6.11.2 Oscillator and Clock System (CS)
The clock system includes support for a 32-kHz watch crystal oscillator XT1 (LF), an internal very-low-
power low-frequency oscillator (VLO), an integrated internal digitally controlled oscillator (DCO), and a
high-frequency crystal oscillator XT2 (HF). The clock system module is designed to meet the requirements
of both low system cost and low power consumption. A fail-safe mechanism exists for all crystal sources.
The clock system module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32-kHz watch crystal (LFXT1), the internal low-frequency
oscillator (VLO), or a digital external low frequency (<50 kHz) clock source.
• Main clock (MCLK), the system clock used by the CPU. MCLK can be sourced from a high-frequency
crystal (HFXT2), the internal digitally-controlled oscillator DCO, a 32-kHz watch crystal (LFXT1), the
internal low-frequency oscillator (VLO), or a digital external clock source.
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules. SMCLK can be
sourced by same sources made available to MCLK.
6.11.3 Power Management Module (PMM)
The primary functions of the PMM are:
• Supply regulated voltages to the core logic
• Supervise voltages that are connected to the device (at DVCC pins)
• Give reset signals to the device during power-on and power-off
Copyright © 2014–2015, Texas Instruments Incorporated
Detailed Description
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