MSP430FR6889 Datasheet, PDF (70/176 Pages) Texas Instruments – Mixed-Signal Microcontrollers

MSP430FR6889, MSP430FR68891, MSP430FR6888, MSP430FR6887
MSP430FR5889, MSP430FR58891, MSP430FR5888, MSP430FR5887
SLASE32A – AUGUST 2014 – REVISED MARCH 2015
www.ti.com
5.13.5.9 FRAM Controller
Table 5-42. FRAM
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
Read and write endurance
TEST
CONDITIONS
MIN
10¹⁵
TYP MAX UNIT
cycles
t_Retention Data retention duration
I_WRITE
I_ERASE
t_WRITE
t_READ
Current to write into FRAM
Erase current
Write time
Read time, NWAITSx=0
Read time, NWAITSx=1
T_J = 25°C
T_J = 70°C
T_J = 85°C
100
40
10
I_READ ⁽¹⁾
n/a ⁽²⁾
t_READ ⁽³⁾
1/f_SYSTEMS ⁽⁴⁾
2/f_SYSTEMS ⁽⁴⁾
years
nA
nA
ns
ns
ns
(1) Writing to FRAM does not require a setup sequence or additional power when compared to reading from FRAM. The FRAM read
current I_READ is included in the active mode current consumption numbers I_AM,FRAM.
(2) FRAM does not require a special erase sequence.
(3) Writing into FRAM is as fast as reading.
(4) The maximum read (and write) speed is specified by f_SYSTEMS using the appropriate wait state settings (NWAITSx).
5.13.6 Emulation and Debug
Table 5-43. JTAG and Spy-Bi-Wire Interface
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN
TYP MAX UNIT
I_JTAG
f_SBW
t_SBW,Low
t_{SBW, En}
Supply current adder when JTAG active (but not clocked)
Spy-Bi-Wire input frequency
Spy-Bi-Wire low clock pulse duration
Spy-Bi-Wire enable time (TEST high to acceptance of first clock
edge) ⁽¹⁾
2.2 V, 3.0 V
2.2 V, 3.0 V
0
2.2 V, 3.0 V 0.04
2.2 V, 3.0 V
40 100 μA
10 MHz
15 μs
110 μs
t_SBW,Rst
f_TCK
Spy-Bi-Wire return to normal operation time
TCK input frequency - 4-wire JTAG⁽²⁾
15
2.2 V
0
3.0 V
0
100 μs
16 MHz
16 MHz
R_internal
f_TCLK
t_{TCLK,Low/High}
f_TCLK,FRAM
t_{TCLK,FRAM,Low/High}
Internal pulldown resistance on TEST
TCLK/MCLK frequency during JTAG access, no FRAM access
(limited by f_SYSTEM)
TCLK low or high clock pulse duration, no FRAM access
TCLK/MCLK frequency during JTAG access, including FRAM access
(limited by f_SYSTEM with no FRAM wait states)
TCLK low or high clock pulse duration, including FRAM accesses
2.2 V, 3.0 V
20
35
50 kΩ
16 MHz
25 ns
4 MHz
100 ns
(1) Tools accessing the Spy-Bi-Wire interface need to wait for the t_SBW,En time after pulling the TEST/SBWTCK pin high before applying the
first SBWTCK clock edge.
(2) f_TCK may be restricted to meet the timing requirements of the module selected.
70
Specifications
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MSP430FR58891 MSP430FR5888 MSP430FR5887